Patent application number | Description | Published |
20090072234 | Test Stuctures for development of metal-insulator-metal (MIM) devices - In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto. | 03-19-2009 |
20090109598 | Metal-insulator-metal (MIM) device and method of formation thereof - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 04-30-2009 |
20090109727 | Erase, programming and leakage characteristics of a resistive memory device - The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art. | 04-30-2009 |
20100208517 | PIN DIODE DEVICE AND ARCHITECTURE - A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line. | 08-19-2010 |
20110027992 | MEMORY DEVICE WITH IMPROVED DATA RETENTION - The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone. | 02-03-2011 |
20110253968 | RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF - An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory deviceāP-I-N diode structures. | 10-20-2011 |
20120081983 | METHOD OF PROGRAMMING, ERASING AND REPAIRING A MEMORY DEVICE - A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor. | 04-05-2012 |
20120276706 | DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE IMPROVED SCALEABILITY - A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer. | 11-01-2012 |
20130237030 | METAL-INSULATOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREOF - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 09-12-2013 |
20140167135 | Process Charging Protection for Split Gate Charge Trapping Flash - A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions. | 06-19-2014 |
20140167140 | Memory First Process Flow and Device - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer. | 06-19-2014 |
20140167141 | Charge Trapping Split Gate Embedded Flash Memory and Associated Methods - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different. | 06-19-2014 |
20140170843 | Charge Trapping Split Gate Device and Method of Fabricating Same - Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device. | 06-19-2014 |
20140301146 | MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS - A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level. | 10-09-2014 |
20140357044 | METAL-INSUALTOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREROF - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. in alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 12-04-2014 |