Patent application number | Description | Published |
20140099785 | Sacrificial Low Work Function Cap Layer - A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer. | 04-10-2014 |
20140175618 | TRANSITION METAL ALUMINATE AND HIGH K DIELECTRIC SEMICONDUCTOR STACK - Methods of forming a high K dielectric semiconductor stack are described. A semiconductor substrate is provided, in which the native oxide layer is removed. A transition metal aluminate layer is deposited onto the semiconductor substrate across discrete multiple regions in a combinatorial manner. A high K dielectric layer is deposited onto the transition metal aluminate layer across the discrete multiple regions in a combinatorial manner. The transition metal aluminate layer and the high K dielectric layer are patterned to form a plurality of high K dielectric semiconductor stacks across discrete multiple regions. A three-five semiconductor substrate or a germanium substrate can be used in methods of forming a high K dielectric semiconductor stack. | 06-26-2014 |
20140179100 | Method to Control Depth Profiles of Dopants Using a Remote Plasma Source - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer. | 06-26-2014 |
20150061027 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities. | 03-05-2015 |
20150093887 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITSI - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeO | 04-02-2015 |
20150093889 | METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeO | 04-02-2015 |
20150093914 | METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeO | 04-02-2015 |