Patent application number | Description | Published |
20100058094 | DATA PROCESSING APPARATUS - A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part. | 03-04-2010 |
20110010508 | Memory system and information processing device - A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory. | 01-13-2011 |
20110314347 | MEMORY ERROR DETECTING APPARATUS AND METHOD - A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison. | 12-22-2011 |
20120254663 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block. | 10-04-2012 |
20130145233 | MEMORY MODULE AND SEMICONDUCTOR STORAGE DEVICE - A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks, and an address scrambling circuit that processes an input address signal and that selects a block to be operated. | 06-06-2013 |
20150155027 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a memory block to include memory cells to hold data; a precharge control unit to control precharging the memory cells; a row decoder to output a row selection signal identifying a row address of the memory cells; an integral circuit to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit to determine whether the integral value of the integral circuit becomes the predetermined value or greater. The precharge control unit turns off precharging the memory cells when the integral value of the integral circuit becomes the predetermined value or greater. | 06-04-2015 |
20150199246 | MEMORY DEVICE, STORAGE METHOD AND CONTROL DEVICE - A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity. | 07-16-2015 |