Patent application number | Description | Published |
20080197420 | Method for fabricating dual-gate semiconductor device - A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions. | 08-21-2008 |
20130217233 | Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing - Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate. | 08-22-2013 |
20130221448 | FIN PROFILE STRUCTURE AND METHOD OF MAKING SAME - A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin. | 08-29-2013 |
20130277759 | Semiconductor Fin Structures and Methods for Forming the Same - A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region. | 10-24-2013 |
20130302975 | Fin Profile Structure and Method of Making Same - A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin. | 11-14-2013 |
20140183661 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate. | 07-03-2014 |
20140252428 | Semiconductor Fin Structures and Methods for Forming the Same - An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope. | 09-11-2014 |
20140256093 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. | 09-11-2014 |
20140273380 | FinFETs with Regrown Source/Drain and Methods for Forming the Same - A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess. | 09-18-2014 |