Patent application number | Description | Published |
20080318534 | TWO-STEP CHANNEL SELECTION FOR WIRELESS TRANSMITTER FRONT-ENDS - A reconfigurable multimode transmitter is disclosed, operating in accordance with a two-step channel selection. The first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver. | 12-25-2008 |
20120194364 | ANALOG-TO-DIGITAL CONVERTING SYSTEM - A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate. | 08-02-2012 |
20120229313 | ANALOG TO DIGITAL CONVERTER CIRCUIT - The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design | 09-13-2012 |
20120286840 | DELAY GENERATOR - A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay. | 11-15-2012 |
20120306679 | N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT - The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DAC | 12-06-2012 |
20140132307 | Comparator and calibration thereof - A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal. | 05-15-2014 |
20140232465 | FREQUENCY COMPENSATION TECHNIQUES FOR LOW-POWER AND SMALL-AREA MULTISTAGE AMPLIFIERS - A three stage amplifier is provided and the three stage amplifier comprises a first gain stage, a second gain stage and a third gain stage wherein said first stage receives an amplifier input signal and said third gain stage outputs an amplifier output signal. The amplifier includes a feedback loop having a current buffer and a compensation capacitance provided from the output of said third gain stage to the output of the first gain stage. In addition, an active left half plane zero stage is embedded in said feedback loop for cancelling a parasitic pole of said feedback loop. | 08-21-2014 |
20140368363 | Sampling front-end for Analog to Digital Converter - A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure. | 12-18-2014 |