Patent application number | Description | Published |
20160125551 | METHOD AND SYSTEM FOR PUBLIC AND PRIVATE TEMPLATE SHARING - A method for sharing templates for use with a financial management application (FMA) includes receiving, from each of multiple financial professionals, a company profile including a chart of accounts for a business operating within a commercial industry and at a geographic location, generating profile templates including, for each profile, a template including the commercial industry, the geographic location, and a redacted chart of accounts of the profile, receiving, from each of the financial professionals, a request to publicly share the template corresponding to the profile, receiving, from a small business representative, a profile creation request specifying a first commercial industry and a first geographic location, identifying a first template, and providing, in response to the profile creation request, the first template to the representative, where the representative uses the first template to create a first profile for the business. | 05-05-2016 |
Patent application number | Description | Published |
20140241028 | TWO-BIT READ-ONLY MEMORY CELL - A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference. | 08-28-2014 |
20140241061 | FAST ACCESS WITH LOW LEAKAGE AND LOW POWER TECHNIQUE FOR READ ONLY MEMORY DEVICES - A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption. | 08-28-2014 |
20150138863 | INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES - An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines. | 05-21-2015 |
20150138864 | MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES - Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines. | 05-21-2015 |
20150138876 | GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES - An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment. | 05-21-2015 |
20150255148 | BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES - SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state. | 09-10-2015 |
20150302918 | WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES - Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path. | 10-22-2015 |
Patent application number | Description | Published |
20150120911 | METHOD AND SYSTEM FOR NETWORK SERVICE HEALTH CHECK AND LOAD BALANCING - A non-transitory computer readable medium includes instructions which, when executed by one or more network devices, causes performance of operations. The operations include sending, to shared devices, one or more status queries regarding one or more device conditions for each of the shared devices, obtaining responses to the one or more status queries from each of the plurality of shared devices, the responses including the one or more device conditions for each of the shared devices, filtering the shared devices based on the one or more device conditions to obtain a subset of the shared devices, identifying the subset of the shared devices as a set of available shared devices, and transmitting information identifying the set of available shared devices to a client device. | 04-30-2015 |
20150120951 | METHOD AND SYSTEM FOR CONTROLLING ACCESS TO SHARED DEVICES - A non-transitory computer readable medium includes computer readable program code including instructions for subsequent to a client device associating with an access point, receiving a request for a set of allowed shared devices, removing, by the access point and to obtain the set of allowed shared devices, a shared device from a set of shared devices based on a client device user of the client device failing to have a permission required by a device sharing policy of the shared device, and transmitting the set of allowed shared devices to the client device. | 04-30-2015 |