Patent application number | Description | Published |
20100058144 | MEMORY SYSTEM WITH ECC-UNIT AND FURTHER PROCESSING ARRANGEMENT - A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors. | 03-04-2010 |
20100287443 | PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS - A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element. | 11-11-2010 |
20110082970 | SYSTEM FOR DISTRIBUTING AVAILABLE MEMORY RESOURCE - A system for distributing available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. | 04-07-2011 |
20110083041 | MEMORY SYSTEM WITH REDUNDANT DATA STORAGE AND ERROR CORRECTION - A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal. | 04-07-2011 |
20110317802 | CLOCK GLITCH DETECTION CIRCUIT - In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment. A comparator determines the difference between the first count and the second count, or determines whether the first count and the second count differ. The synchronous circuit may comprise the first circuit. A second circuit for detecting clock glitches in a clock signal is also provided. The second circuit is intended to be integrated in the synchronous circuit. | 12-29-2011 |
20120304024 | DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR - A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy. | 11-29-2012 |
20130181696 | LOW-VOLTAGE EXIT DETECTOR, ERROR DETECTOR, LOW-VOLTAGE SAFE CONTROLLER, BROWN-OUT DETECTION METHOD, AND BROWN-OUT SELF-HEALING METHOD - A low-voltage exit detector comprises a low-voltage detector and a voltage rise detector for detecting a change from a low-voltage condition of a watched voltage to a non-low-voltage condition of the watched voltage. An error detector for detecting storage errors comprises: a low-voltage exit detector as described above, first and second loaders for loading an load-ing information into first and second storage elements, wherein the loading information is coded using first and second coding schemes; first and second retrievers for retrieving stored information stored in the first and the second storage elements and decoding this information; and a second comparator for comparing a combination of a first retrieved information retrieved using the first retriever and a second retrieved information retrieved using the second retriever to each pattern of a set of valid patterns and for generating a match-mismatch signal indicating a result of this comparison. Further, the invention relates to a low-voltage safe controller comprising an error de-tector as described above and an application unit, to a brown-out detection method, and to a brown-out self-healing method. | 07-18-2013 |
20140006841 | CLOCK GLITCH DETECTION CIRCUIT | 01-02-2014 |
20140173353 | INTEGRATED CIRCUIT DEVICE AND METHOD OF IDENTIFYING A PRESENCE OF A BROKEN CONNECTION WITHIN AN EXTERNAL SIGNAL PATH - An integrated circuit device comprises at least one connectivity identification module. The at least one connectivity identification module is arranged to determine an initial sensed state of at least one external signal path of the integrated circuit device, cause the at least one external signal path to be pulled towards an opposing state to the initial sensed state therefor, determine a new sensed state of the at least one external signal path of the integrated circuit device, and identify a presence of a broken connection within the at least one external signal path, if the new sensed state of the at least one external signal path does not match the initial sensed state of the at least one external signal path. | 06-19-2014 |
20140189462 | ERROR CORRECTING DEVICE, METHOD FOR MONITORING AN ERROR CORRECTING DEVICE AND DATA PROCESSING SYSTEM - An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal. | 07-03-2014 |
Patent application number | Description | Published |
20140179083 | HIGH DIE STRENGTH SEMICONDUCTOR WAFER PROCESSING METHOD AND SYSTEM - Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described. | 06-26-2014 |
20140264768 | Die Preparation for Wafer-Level Chip Scale Package (WLCSP) - Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded. | 09-18-2014 |
20150069578 | COMBINATION GRINDING AFTER LASER (GAL) AND LASER ON-OFF FUNCTION TO INCREASE DIE STRENGTH - Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil. | 03-12-2015 |