Patent application number | Description | Published |
20090322577 | LOW-POWER COLUMN PARALLEL CYCLIC ANALOG-TO-DIGITAL CONVERTER - A low-power column parallel cyclic analog-to-digital converter and an imaging device using the same. The analog-to-digital converter comprises one stage and is optimized to reduce power, noise and capacitor settling time. The one stage analog-to-digital converter comprises a multiplying circuit for performing a multiplication operation during conversion phases and a sub-analog-to-digital converter connected to receive analog output signals from the multiplying circuit. The sub-analog-to-digital converter converts, during the conversion phases, the analog output signals into portions of an N-bit digital code. The multiplying circuit switches configurations between conversion phases and uses the portions of the digital code during the conversion phases to generate new analog output signals for subseQuent conversion by the sub-analog-to-digital converter. | 12-31-2009 |
20100002094 | Method and apparatus providing multiple exposure high dynamic range sensor - Imagers reproduce an image by converting photons to a signal that is representative of the image. A sensor readout module reads reset and signal voltages corresponding to a plurality of integration times for each of a plurality of pixels. The sensor readout module is capable of determining whether the differences between reset and signal voltages corresponding to respective integration times indicate a saturation condition of the pixel. Accordingly, the sensor readout module may provide an output signal based on reset and signal voltages corresponding to an integration time that is less than an integration time for reset and signal voltages that indicate the saturation condition. A normalization module may normalize the output signal to correspond with a linear response curve. | 01-07-2010 |
20100237939 | ADAPTIVE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER LOAD COMPENSATION - A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The buffer includes an operational amplifier having an output stage of multiple transistors, selectively connected in parallel. During operation, data regarding the size of the capacitive load is obtained and used to determine the size of the output stage. In general, as the capacitive load increases, the number of transistors connected in parallel at the output stage also increases. | 09-23-2010 |
20130057422 | COMPARATOR NOISE REDUCTION BY MEANS OF A PROGRAMMABLE BANDWIDTH - A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals. | 03-07-2013 |
20140048686 | CAPACITANCE SELECTABLE CHARGE PUMP - A step-up converter includes an input coupled to receive a first voltage potential and an output coupled to output a second voltage potential higher than the first voltage potential. The step-up converter also includes an array of capacitance charge pumps. Each of the capacitance charge pumps in the array includes switches to be modulated to individually run each of the capacitance charge pumps by selectively connecting each of the capacitance charge pumps to the input and the output. The step-up converter further includes a control module coupled to the switches of each of the capacitance charge pumps and configured to modulate the switches at a substantially fixed frequency. The control module modulates the switches of selected capacitance charge pumps in the array in response to a current draw on the output. The step-up converter may be included in an image sensor. | 02-20-2014 |
20140183333 | CONVERSION CIRCUITRY FOR REDUCING PIXEL ARRAY READOUT TIME - An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register (“SAR”) analog-to-digital-converter (“ADC”), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array (“FCA”) that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array (“SCA”) that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage. | 07-03-2014 |
20140345873 | TUBING HANGER WITH COUPLING ASSEMBLY - A tubing hanger ( | 11-27-2014 |