Rengang
Rengang Chen, Hellertown, PA US
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20130154590 | SYSTEMS AND METHODS FOR REGULATING A SWITCHING CONVERTER - Systems and methods for regulating a switching converter are disclosed. One embodiment of the present invention relates to a power supply system that comprises a switching converter that provides an output voltage by alternately turning on and off a high-side transistor and a low-side transistor both coupled to an output inductor through a switching node. The switching converter includes a drive circuit that regulates the output voltage based on a feedback signal. The power supply system also comprises a simulated output generator that generates and provides the drive circuit with a simulated inductor waveform as the feedback signal based on a low-side output waveform of the low-side transistor measured at the switching node during off-times of the switching converter. | 06-20-2013 |
Rengang Li, Beijing CN
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20130346933 | PROTOTYPE VERIFICATION SYSTEM AND VERIFICATION METHOD FOR HIGH-END FAULT-TOLERANT COMPUTER - A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets. | 12-26-2013 |
20130346934 | HIGH-END FAULT-TOLERANT COMPUTER SYSTEM AND METHOD FOR SAME - The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system. | 12-26-2013 |
Rengang Li, Jinan City CN
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20150067631 | DESIGN METHOD OF REPEATER CHIP - A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit. | 03-05-2015 |