Patent application number | Description | Published |
20130207158 | SEMICONDUCTOR DEVICE - To improve a manufacture yield of semiconductor devices each including an IGBT, an active region defined by an insulating film and where an element of an IGBT is formed has a first long side and a second long side spaced at a predetermined distance apart from each other and extended in a first direction in a planar view. One end of the first long side has a first short side forming a first angle with the first long side, and one end of the second long side has a second short side forming a second angle with the second long side. The other end of the first long side has a third short side forming a third angle with the first long side, and the other end of the second long side has a fourth short side forming a fourth angle with the second long side. The first angle, the second angle, the third angle, and the fourth angle are in a range larger than 90 degrees and smaller than 180 degrees. | 08-15-2013 |
20130207164 | SEMICONDUCTOR DEVICE - To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR | 08-15-2013 |
20130207203 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed. | 08-15-2013 |
20130207228 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film. | 08-15-2013 |
20130207245 | METHODS FOR MAKING POROUS INSULATING FILMS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding. | 08-15-2013 |
20130207252 | Semiconductor Device - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 08-15-2013 |
20130207256 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. | 08-15-2013 |
20130207259 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND WAFER - The present invention prevents bumps on semiconductor chips from sticking to probe needles and coming off from the semiconductor chips. A wafer has effective areas where a plurality of bumps (first bumps) are formed. The bumps are formed on the side of an active surface of the semiconductor chips. The wafer further has non-effective areas where a plurality of dummy bumps are formed. Among the dummy bumps, some positioned at the outermost circumference are dummy bumps (second bumps) that are smaller than the other bumps. The dummy bumps (second bumps) intersect the inner peripheral edge of a shielding member as viewed in a plan view. The dummy bumps (second bumps) are formed over third pad electrodes. A bump-formation insulating film is removed from over the entire third pad electrodes. | 08-15-2013 |
20130207269 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face. | 08-15-2013 |
20130207959 | Liquid Crystal Display Controller - The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone. | 08-15-2013 |
20130211831 | SEMICONDUCTOR DEVICE AND VOICE COMMUNICATION DEVICE - A semiconductor device for realizing higher-precision noise elimination includes: a decoder which decodes an encoded input signal; a determining unit which determines whether or not a voice signal is included in the input signal; a suppressor which performs a suppressing process for suppressing a noise component included in the input signal on the basis of a result of determination by the determining unit; and a first storage for storing, as a determination criterion value used for the determination, a first criterion value which specifies the proportion of a voice signal with respect to voice distortion noise. | 08-15-2013 |
20130212362 | IMAGE PROCESSING DEVICE AND DATA PROCESSOR - A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit. | 08-15-2013 |
20130214337 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed. | 08-22-2013 |
20130214339 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part. | 08-22-2013 |
20130214348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a vertical transistor, to raise a drain withstand voltage while lowering an on-resistance. A drift layer | 08-22-2013 |
20130214378 | SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION - A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes. | 08-22-2013 |
20130214428 | SEMICONDUCTOR DEVICE HAVING NON-PLANAR INTERFACE BETWEEN A PLUG LAYER AND A CONTACT LAYER - A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer. | 08-22-2013 |
20130214753 | CONTROL DEVICE, DIGITAL CONTROL POWER SUPPLY, AND CONTROL METHOD - In a digital control power supply, a mode control unit measures a first frequency and a second frequency for a difference between a second digital value and a target value. Based on the measured first frequency and second frequency and a predetermined threshold set to the first and second frequencies, the mode control unit determines whether an amplification factor for use in amplification processing by an amplifier is maintained at a current amplification factor or is changed to an amplification factor which is larger or smaller by 1 than the current amplification factor. This contributes to an improvement in noise resistance of the digital control power supply and prevents an output voltage from being unstable. | 08-22-2013 |
20130214846 | SEMICONDUCTOR DEVICE - The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal. | 08-22-2013 |
20130214869 | TEMPERATURE-COMPENSATED SEMICONDUCTOR RESISTOR DEVICE - A semiconductor device includes: a resistance R whose resistance value varies in response to a substrate temperature variation; a resistance corrector that is coupled in series with the resistance R and switches its resistance value by a preset resistance step width to suppress a resistance value variation of the resistance R; a first voltage generator for generating a first voltage that varies in response to the substrate temperature; a second voltage generator for generating second voltages Vf | 08-22-2013 |
20130214946 | A/D Converter and Method for Calibrating the Same - An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal. | 08-22-2013 |
20130214947 | Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit - A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal. | 08-22-2013 |
20130215020 | SIGNAL PROCESSING DEVICE AND SEMICONDUCTOR DEVICE - To restrain the amount of information to be saved to the minimum necessary and suppress temporal overhead required for save and return when task switching associated with a priority processing request occurs in a signal processing device for performing multitasking on stream data such as image signals, the signal processing device includes a pointer indicating position information of data in stream data according to progress of processing by a signal processing unit. When priority task processing is requested, the signal processing device saves only a pointer value. At the time of return, based on the saved pointer value the signal processing device obtains position information of output stream data to be outputted next in a returned task, obtains position information, in an input stream, of head input data of all input data that needs to be inputted to the signal processing unit to calculate the data, and resumes the processing. | 08-22-2013 |
20130219095 | CIRCUIT AND METHOD FOR PIPE ARBITRATION USING AVAILABLE STATE INFORMATION AND ARBITRATION - Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. | 08-22-2013 |
20130219352 | LSI DESIGN METHOD - Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs. | 08-22-2013 |
20130221508 | SEMICONDUCTOR DEVICE SEALED WITH A RESIN MOLDING - An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's. | 08-29-2013 |
20130221520 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm. | 08-29-2013 |
20130221538 | SEMICONDUCTOR DEVICE - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. | 08-29-2013 |
20130222038 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition. | 08-29-2013 |
20130222048 | POWER DEVICE - A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit. Each of the output cells includes an output transistor. First side electrodes of the output transistors are commonly coupled to a first power source. Each of second side electrodes of the output transistors is coupled to an output terminal through the corresponding bonding wire. The control terminal driving circuit supplies a drive signal to the control terminals of the individual output transistors to control the output transistors. Each of the bonding wires is designed to be fused and cut if the output transistor included in the corresponding output cell fails and is shorted. | 08-29-2013 |
20130223164 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. | 08-29-2013 |
20130224891 | MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - Parts of electronic components are not exposed to temperature deviating from an appropriate operation temperature range when an electric characteristic test of a semiconductor module having an interposer substrate over which plural kinds of electronic components are mounted is carried out. A heat sink for an electronic component is incorporated in a lid of a test socket used for an electric characteristic test of an MCM. A heat dissipation sheet is attached to part of the bottom face of the heat sink and an adiabatic sheet is attached to another part. The heat dissipation sheet has thermal conductivity larger than the adiabatic sheet and transfers heat generated from an electronic component of a high heat value to the heat sink during operation. The adiabatic sheet inhibits the heat generated from an electronic component of high heat value from being transferred to another electronic component through the heat sink. | 08-29-2013 |
20130224947 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 08-29-2013 |
20130227505 | Equivalence Checking Method, Equivalence Checking Program, and Equivalence Checking Device - Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used. | 08-29-2013 |
20130272058 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 10-17-2013 |
20130307036 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern Pla is formed in the same layer as that of a second layer wiring and the pattern Pib is formed in the same layer as that of a first layer wiring. Further, the pattern P | 11-21-2013 |
20140002135 | SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION MODES AND OPERATION MODE SETTING METHOD THEREFOR | 01-02-2014 |