Patent application number | Description | Published |
20120159285 | STORAGE DRIVE WITH LDPC CODING - For storage drives with LDPC encoded data, read techniques are provided whereby an errantly read memory unit (e.g., faulty LDPC codeword) may be recovered. | 06-21-2012 |
20130318395 | RECONSTRUCTING CODEWORDS USING A SIDE CHANNEL - Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory (“NVM”) have failed iterative decoding. In various embodiments, the memory controller may be further configured to generate a side channel from n-m non-failed die and the m failed die other than a first failed die. In various embodiments, the memory controller may be further configured to reconstruct, using iterative decoding, a codeword stored on the first failed die of the m failed die based on the generated side channel and on soft input to an attempt to iteratively decode data stored on the first failed die. In various embodiments, the iterative decoding may include low-density parity-check decoding. Other embodiments may be described and/or claimed. | 11-28-2013 |
20140089561 | Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory - Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed. | 03-27-2014 |
20140115231 | NAND MEMORY MANAGEMENT - Apparatus, systems, and methods manage NAND memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string. Other embodiments are also disclosed and claimed. | 04-24-2014 |
20140119114 | CENTER READ REFERENCE VOLTAGE DETERMINATION BASED ON ESTIMATED PROBABILITY DENSITY FUNCTION - Embodiments include systems, methods, and apparatuses to estimate respective first and second cumulative density functions (CDFs) for values of a plurality of non-volatile memory (NVM) cells in a page of memory. The CDFs may be based at least in part on one or more decoder outputs of codewords for data stored in the page. Based at least in part on the CDFs, first and second probability density functions (PDFs) may be estimated for the values of the page of memory. A center read reference voltage may then be determined for reading a cell in the page. The center read reference voltage may be based at least in part on the first and second PDFs. | 05-01-2014 |
20140122963 | IDENTIFICATION OF NON-VOLATILE MEMORY DIE FOR USE IN REMEDIAL ACTION - Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die. | 05-01-2014 |
20140122973 | DISTRIBUTED CODEWORD PORTIONS - Embodiments of the present disclosure describe apparatus, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple memory components. For example, a device may include non-volatile memory (“NVM”) including m die. A memory controller may be configured to store portions of an ECC codeword among the m die. In various embodiments, a memory controller and/or an iterative decoder such as a low-density parity-check (“LDPC”) decoder may be configured to decode ECC codewords based at least in part on reliability metrics associated with the m die. Other embodiments may be described and/or claimed. | 05-01-2014 |
20140149825 | SCALING FACTORS FOR HARD DECISION READS OF CODEWORDS DISTRIBUTED ACROSS DIE - Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword. | 05-29-2014 |
20140245096 | SINGLE-BIT ERROR CORRECTION - Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed. | 08-28-2014 |
20140247655 | MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY DATA READING METHOD AND APPARATUS - Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells. | 09-04-2014 |
20150089310 | USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY - Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed. | 03-26-2015 |