Patent application number | Description | Published |
20080218205 | Timing Exact Design Conversions from FPGA to ASIC - A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts. | 09-11-2008 |
20090004788 | THIN FILM TRANSISTORS AND FABRICATION METHODS - A method of fabricating a low temperature semiconductor thin film device is described. The method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line; forming a thin film device having: a first amorphous silicon region, wherein a portion of the region covers a said conductive contact; and a gate dielectric layer; and a second amorphous silicon layer; forming a silicide of first and second amorphous silicon material with a deposited metallic material; depositing an insulating material; and forming conductive contacts and top metal interconnects to couple said first and second amorphous silicon regions. | 01-01-2009 |
20090004791 | SEMICONDUCTOR SWITCHING DEVICES AND FABRICATION METHODS - Methods of fabricating low temperature semiconductor thin film switching devices are described. A method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line thru an insulator layer above the metal lines; forming a thin film N-type and P-type conducting transistor pair having: a contiguous amorphous silicon first geometry above the insulator layer, said first geometry including an N-type transistor region, a P-type transistor region, and a common region between the transistor regions fully covering the contact; and a gate dielectric layer above the first geometry; and a contiguous amorphous silicon second geometry above the gate dielectric layer including transistor regions that cross over the first geometry transistor regions; forming a silicide of first and second amorphous silicon geometry surfaces with a deposited metallic material, the silicided surfaces including: said second geometry surface; and said first geometry surface not covered by the second geometry, which includes the surface of the region covering the contact; depositing an insulating material; and forming conductive contacts and top metal interconnects. | 01-01-2009 |
20090039917 | Programmable Interconnect Structures - A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. | 02-12-2009 |
20090039918 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A programmable integrated circuit (IC), comprising: a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and a first plurality of read only memory (ROM) elements capable of coupling to the first control signal, wherein a said first ROM elements is selected to couple by one or more decode signals, and wherein the first ROM elements store a plurality of user specifications. | 02-12-2009 |
20090128188 | Pad invariant FPGA and ASIC devices - A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks. | 05-21-2009 |
20090128189 | Three dimensional programmable devices - In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements. | 05-21-2009 |
20090134909 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element is positioned above a transistor material layer deposited on a substrate layer. | 05-28-2009 |
20090146189 | Pads and pin-outs in three dimensional integrated circuits - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array. | 06-11-2009 |
20090243650 | PROGRAMMABLE LOGIC DEVICES COMPRISING TIME MULTIPLEXED PROGRAMMABLE INTERCONNECT - A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval. | 10-01-2009 |
20100070942 | Automated Metal Pattern Generation for Integrated Circuits - An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively. | 03-18-2010 |
20100207660 | PROGRAMMABLE LOGIC DEVICES COMPRISING TIME MULTIPLEXED PROGRAMMABLE INTERCONNECT - A time multiplex logic device is disclosed. The device comprises a single wire segment to couple a plurality of logic outputs to a plurality of logic inputs using a non-overlapping time multiplex sequence of global controls signals. The disclosure includes programmable logic blocks and wire structures that allow wire sharing. Time shared wires offer significant reduction in total wires needed for routing in programmable logic, which accounts for the single largest overhead and cost associated with programmable logic. | 08-19-2010 |
20110074464 | LOW POWER PROGRAMMABLE LOGIC DEVICES - Circuits and power up sequences to reduce power consumption in programmable logic devices is disclosed. A multiplexer (MUX) for a programmable logic device comprising: a plurality of inputs and an output; and a configuration circuit comprising a plurality of memory elements, each memory element generating a control signal, the configuration circuit comprising a first mode of operation to force each of said control signals to a first voltage level regardless of the memory state in the memory element; and a first device coupling a power supply voltage to the output, said first device having a gate electrode controlled by a said control signal of the configuration circuit; and one or more second devices coupling one or more inputs to the output, each said second device having a gate electrode controlled by a said control signal of the configuration circuit; wherein, the first device is in a conducting state to couple the power supply voltage to the MUX output during the first mode of operation of the configuration circuit. | 03-31-2011 |
20110102014 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers. | 05-05-2011 |
20120119782 | Logic for Metal Configurable Integrated Circuits - A metal programmable logic unit of a semiconductor device is disclosed. The programmable logic unit comprises: an interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plurality of selectable interconnect geometries, each selectable geometry coupling a said first fixed interconnect to a said second fixed interconnect; and a programmable logic block comprising a plurality of multiplexers, each multiplexer having a plurality of regular inputs, wherein each said regular input is selectively coupled to one of a zero state, a one state, a first input state, and the compliment of the first input state; and a programmable multiplexer having a plurality of regular inputs, wherein each said regular inputs is selectively coupled to one of a zero state, a one state, and one or more input signals; wherein, selecting a subset of the selectable interconnect geometries program the logic block and the multiplexer regular inputs to implement a logic function. | 05-17-2012 |
20120286822 | AUTOMATED METAL PATTERN GENERATION FOR INTEGRATED CIRUCITS - An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively. | 11-15-2012 |
20120319728 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer. | 12-20-2012 |
20130002296 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer. | 01-03-2013 |
20140117413 | PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array. | 05-01-2014 |
20150077159 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer. | 03-19-2015 |