Patent application number | Description | Published |
20130044552 | STROBE-OFFSET CONTROL CIRCUIT - A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal. | 02-21-2013 |
20130064023 | Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data to Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. | 03-14-2013 |
20130094310 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 04-18-2013 |
20130097403 | Address Mapping in Memory Systems - A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address. | 04-18-2013 |
20130114363 | MULTI-MODAL MEMORY INTERFACE - A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques. | 05-09-2013 |
20130121094 | INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP - Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry. | 05-16-2013 |
20130132685 | MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL - Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers. | 05-23-2013 |
20130138911 | MEMORY CONTROLLER WITH RECONFIGURABLE HARDWARE - Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits ( | 05-30-2013 |
20130148437 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 06-13-2013 |
20130162460 | HIGH-ACCURACY DETECTION IN COLLABORATIVE TRACKING SYSTEMS - An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons. The processing circuitry couples to the transceiver circuitry and tracks the position of the second device based on the modulated reflected beacons. | 06-27-2013 |
20130168674 | Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits - A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive. | 07-04-2013 |
20130176763 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. | 07-11-2013 |
20130176800 | MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE - A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. | 07-11-2013 |
20130182457 | LIGHTING ASSEMBLY WITH STATIC AUTOSTEREOSCOPIC IMAGE OUTPUT - A lighting assembly includes a light guide in which light propagates by total internal reflection between opposed major surfaces. The light guide receives light generated by two light sources at opposed light input edges of the light guide. The light guide includes light extracting elements that respectively extract light to form a left eye image at a first region and a right eye image at a second region. The left eye and right eye images, when viewed by a viewer, form a static autostereoscopic image. | 07-18-2013 |
20130188436 | INTEGRATED CIRCUIT WITH ADAPTIVE POWER STATE MANAGEMENT - Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: ( | 07-25-2013 |
20130194854 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 08-01-2013 |
20130194879 | Early Read After Write Operation Memory Device, System And Method - A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. | 08-01-2013 |
20130202061 | REFERENCE VOLTAGE GENERATION IN A SINGLE-ENDED RECEIVER - As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal. As a result, the receiver provides for reading received single-ended data in a manner enabling accurate data transfer at higher speeds. | 08-08-2013 |