Patent application number | Description | Published |
20090206484 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE - Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line. | 08-20-2009 |
20090242869 | SUPER LATTICE/QUANTUM WELL NANOWIRES - Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire. | 10-01-2009 |
20090302353 | STRUCTURES CONTAINING ELECTRODEPOSITED GERMANIUM AND METHODS FOR THEIR FABRICATION - Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits. | 12-10-2009 |
20100213073 | BATH FOR ELECTROPLATING A I-III-VI COMPOUND, USE THEREOF AND STRUCTURES CONTAINING SAME - A bath for electroplating a I-III-VI compound comprising: water; a copper containing precursor dissolved in said water; a selenium containing precursor dissolved in said water; and at least one member selected from the group consisting of an indium containing precursor dissolved in said water, a gallium containing precursor dissolved in said water and mixtures thereof, and at least one member selected from the group consisting of sulfur-containing organic compound dissolved in said water wherein one or more sulfur atoms directly bond with at least one carbon atom, a phosphorus-containing organic compound dissolved in said water wherein one or more phosphorus atoms directly bond with at least one carbon atom and mixtures thereof is provided along with its use to fabricate thin films, solar devices and tuned thin films. | 08-26-2010 |
20100323517 | MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE - Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line. | 12-23-2010 |
20120286236 | SUPER LATTICE/QUANTUM WELL NANOWIRES - Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire. | 11-15-2012 |
20120305066 | USE OF METAL PHOSPHORUS IN METALLIZATION OF PHOTOVOLTAIC DEVICES AND METHOD OF FABRICATING SAME - A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided. | 12-06-2012 |
20120318341 | PROCESSES FOR UNIFORM METAL SEMICONDUCTOR ALLOY FORMATION FOR FRONT SIDE CONTACT METALLIZATION AND PHOTOVOLTAIC DEVICE FORMED THEREFROM - Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided. In one embodiment, a method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate; forming a plurality of patterned antireflective coating layers on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger regions; forming a mask atop the plurality of patterned antireflective coating layers, the mask having a shape that mimics each patterned antireflective coating; electrodepositing a metal layer on the busbar region and the finger regions; removing the mask; and performing an anneal, wherein during the anneal metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy. | 12-20-2012 |
20130014812 | PHOTOVOLTAIC DEVICE WITH ALUMINUM PLATED BACK SURFACE FIELD AND METHOD OF FORMING SAMEAANM Fisher; Kathryn C.AACI BrooklynAAST NYAACO USAAGP Fisher; Kathryn C. Brooklyn NY USAANM Huang; QiangAACI Sleepy HollowAAST NYAACO USAAGP Huang; Qiang Sleepy Hollow NY USAANM Papa Rao; Satyavolu S.AACI PoughkeepsieAAST NYAACO USAAGP Papa Rao; Satyavolu S. Poughkeepsie NY USAANM Yeh; Ming-LingAACI BaltimoreAAST MDAACO USAAGP Yeh; Ming-Ling Baltimore MD US - A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed. | 01-17-2013 |
20150079723 | Pressure Transfer Process for Thin Film Solar Cell Fabrication - In one aspect, a method for fabricating a thin film solar cell includes the following steps. A first absorber material is deposited as a layer A on a substrate while applying pressure to the substrate/layer A. A second absorber material is deposited as a layer B on layer A while applying pressure to the substrate/layer B. A third absorber material is deposited as a layer C on layer B while applying pressure to the substrate/layer C. A fourth absorber material is deposited as a layer D on layer C while applying pressure to the substrate/layer D. The first absorber material comprises copper, the second absorber material comprises indium, the third absorber material comprises gallium, and the fourth absorber material comprises one or more of sulfur and selenium, and wherein by way of performing the steps of claim | 03-19-2015 |