Patent application number | Description | Published |
20100014746 | INTERACTIVE USER INTERFACES AND METHODS FOR VIEWING LINE TEMPERATURE PROFILES OF THERMAL IMAGES - An interactive graphical user interface includes a moveable pointer, which may be activated to select points of a computer-generated thermal image of an object, as the pointer is moved over a display of the image, so that line temperature profiles, which correspond to predetermined lines extending through the selected points, may be viewed, for example, on a line temperature profile chart of the interface, for each selected point as the pointer is moved. Each predetermined line extends between the corresponding selected point and another, predetermined, point of the image. The other predetermined point may either coincide with an origin of an x-axis or a y-axis of an orthogonal coordinate system, in which the image is aligned, or may be any other point of the thermal image, for example, one that is pre-selected by a user, with the moveable pointer. | 01-21-2010 |
20120075309 | System And Method For Configuring A Thermal Imaging Instrument - A graphical user interface for configuring parameters associated with a portable infrared imager is provided. The interface can be used to manually or automatically set range and span parameters. The interface can also be used to configure one or more alarms to notify a user that a detected temperature is outside a predetermined range. In some embodiments, a non-linear temperature scale can be displayed. | 03-29-2012 |
20120320189 | THERMAL IMAGER THAT ANALYZES TEMPERATURE MEASUREMENT CALCULATION ACCURACY - A method and computer program product for determining whether an object of interest can have its temperature measurement calculated by a thermal imaging camera. To do this, the distance between the camera and the object of interest is measured, then a measurement IFOV is calculated using the measure distance. The measurement IFOV may be displayed on the screen of the camera as a graphical indicator of the object of interest can be registered with the graphical indicator and then it is determined whether the temperature measurement of the object can be acceptably calculated. | 12-20-2012 |
20130083199 | THERMAL IMAGING CAMERA WITH INFRARED LENS FOCUS ADJUSTMENT - A thermal imaging camera may be used to capture a visible-light (VL) image and an infrared (IR) image. In some examples, the camera includes adjustable focus IR optics. For example, the camera may include a focus mechanism coupled to the IR optics and configured to move the IR optics to various focus positions so as to focus the IR optics. The various focus positions may include a hyperfocal position in which a scene is in focus between a set distance and infinity, and a plurality of focus positions in which the scene is in focus between the set distance and a minimum focus distance. Depending on the configuration of the camera, the IR optics of the camera may define an F-number greater than 1.0, and an axis of the IR optics may be offset from an axis of the VL optics by a distance less than 1.7 inches. | 04-04-2013 |
20140028854 | THERMAL IMAGING CAMERA WITH GRAPHICAL TEMPERATURE PLOT - Methods and apparatus for monitoring a temperature of an object over time using a thermal imaging camera. The methods and apparatus may gather infrared temperature data from a selected source of temperature data within a scene at a selected time interval and display a graphical plot of the gathered temperature data on a digital display. | 01-30-2014 |
20140042319 | THERMAL IMAGING CAMERA WITH INTERMITTENT IMAGE CAPTURE - A thermal imaging camera that intermittently captures thermal images of a scene for long term monitoring of the scene. The thermal images may be captured after each interval of a time delay interval and/or upon detection of a threshold change in thermal energy in the scene. | 02-13-2014 |
20140176725 | THERMAL IMAGER THAT ANALYZES TEMPERATURE MEASUREMENT CALCULATION ACCURACY - A method and computer program product for determining whether an object of interest can have its temperature measurement calculated by a thermal imaging camera. To do this, the measurement IFOV is converted into linear units. The measurement IFOV may be displayed on the display of the camera as a graphical indicator ( | 06-26-2014 |
20150269742 | VISIBLE LIGHT IMAGE WITH EDGE MARKING FOR ENHANCING IR IMAGERY - The invention relates generally to edge detection and presentation in thermal images. Infrared and visible light images comprising at least partially overlapping target scenes are analyzed. An edge detection process is performed on the visible light image to determine which pixels represent edges in the target scene. A display image is generated in which some pixels include infrared image data and in which pixels corresponding to edges in the visible light image include a predetermined color and do not include corresponding infrared image data to emphasize edges. Edge pixels in the display image can include exclusively the predetermined color, or in some examples, a blend of a predetermined color and visible light image data. Methods can include replacing one or the other of visible light edge pixels or corresponding infrared pixels with the predetermined color before combining the visible light and infrared image data to create a display image. | 09-24-2015 |
Patent application number | Description | Published |
20100272386 | OPTICALLY AND ELECTRICALLY ACTUATABLE DEVICES - Disclosed herein are optically and electrically actuatable devices. The optically and electrically actuatable device includes an insulating substrate, two electrodes, an active region, and a concentrator. At least one of the two electrodes is established on the insulating substrate, and another of the two electrodes is established a spaced distance vertically or laterally from the at least one of the two electrodes. The other of the two electrodes is an optical input electrode. The active region is established between or beneath the two electrodes. The concentrator is optically coupled to the optical input electrode for concentrating incident light such that a predetermined portion of the active region is optically actuatable. | 10-28-2010 |
20110095774 | TESTING A NONVOLATILE CIRCUIT ELEMENT HAVING MULTIPLE INTERMEDIATE STATES - A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element. | 04-28-2011 |
20110169136 | CROSSBAR-INTEGRATED MEMRISTOR ARRAY AND METHOD EMPLOYING INTERSTITIAL LOW DIELECTRIC CONSTANT INSULATOR - A memristor crossbar array and method of making employ an interstitial insulator. The memristor crossbar array includes a plurality of memristors in an array. The memristors include columns of memristor material disposed between and connecting to a first plurality of wire electrodes and a second plurality of wire electrodes at cross points between the respective wire electrodes. The memristor crossbar array further includes an insulator of a solid material in an interstitial space between the wire electrodes of the first plurality and between the columns of memristor material. The insulator isolates the memristors from one another and has a dielectric constant that is lower than a dielectric constant of the memristor material. The method of making includes forming the plurality of memristors and filling the interstitial space between adjacent memristors with the insulator material. | 07-14-2011 |
20110181347 | MEMRISTOR-PROTECTION INTEGRATED CIRCUIT AND METHOD FOR PROTECTION OF A MEMRISTOR DURING SWITCHING - A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor. | 07-28-2011 |
20110227030 | Memristor Having a Triangular Shaped Electrode - A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode. | 09-22-2011 |
20110227045 | Voltage-Controlled Switches - A voltage-controlled switch ( | 09-22-2011 |
20110240941 | Silicon-Based Memristive Device - A memristive device ( | 10-06-2011 |
20110261608 | Self-Repairing Memristor and Method - A self-repairing memristor ( | 10-27-2011 |
20110266515 | MEMRISTIVE SWITCH DEVICE - A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes. | 11-03-2011 |
20110303890 | Electrically Actuated Device - An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein. | 12-15-2011 |
20120014161 | Memristive Negative Differential Resistance Device - A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material. | 01-19-2012 |
20120032134 | Memristive Junction with Intrinsic Rectifier - A memristive junction ( | 02-09-2012 |
20120057390 | MEMORY ARRAY WITH WRITE FEEDBACK - A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance. | 03-08-2012 |
20120063197 | SWITCHABLE JUNCTION WITH AN INTRINSIC DIODE FORMED WITH A VOLTAGE DEPENDENT RESISTOR - A switchable junction ( | 03-15-2012 |
20120099362 | MEMORY ARRAY WITH METAL-INSULATOR TRANSITION SWITCHING DEVICES - A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series with an MIT material. A method of accessing a target memory element within a memory array includes applying half of an access voltage to a row line connected to the target memory element, the target memory element comprising a switching layer in series with an MIT material, and applying an inverted half of the access voltage to a column line connected to the target memory element. | 04-26-2012 |
20120104346 | SEMICONDUCTOR DEVICE FOR PROVIDING HEAT MANAGEMENT - A semiconductor device for providing heat management may include a first electrode with low metal thermal conductivity and a second electrode with low metal thermal conductivity. A metal oxide structure which includes a transition metal oxide (TMO) may be electrically coupled to the first electrode and second electrode and the metal oxide structure may be disposed between the first electrode and second electrode. An electrically insulating sheath with low thermal conductivity may surround the metal oxide structure. | 05-03-2012 |
20120105159 | MEMRISTIVE PROGRAMMABLE FREQUENCY SOURCE AND METHOD - A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output. | 05-03-2012 |
20120127780 | MEMORY RESISTOR ADJUSTMENT USING FEEDBACK CONTROL - Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings. | 05-24-2012 |
20120138885 | ELECTRICAL CIRCUIT COMPONENT - An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second electrodes are connected to the NDR material and the NDR material is to electrically connect the first electrode to one of the plurality of second electrodes when a sufficient voltage is applied between the first electrode and the one of the plurality of second electrodes through the NDR material. | 06-07-2012 |
20120249252 | OSCILLATOR CIRCUITRY HAVING NEGATIVE DIFFERENTIAL RESISTANCE - Circuitry is provided that closely emulates biological neural responses. Two astable multivibrator circuits (AMCs), each including a negative differential resistance device, are coupled in series-circuit relationship. Each AMC is characterized by a distinct voltage-dependant time constant. The circuitry exhibits oscillations in electrical current when subjected to a voltage equal to or greater than a threshold value. Various oscillating waveforms can be produced in accordance with voltages applied to the circuitry. | 10-04-2012 |
20130099187 | MULTILAYER STRUCTURE BASED ON A NEGATIVE DIFFERENTIAL RESISTANCE MATERIAL - A multilayer structure is disclosed that includes a conductive layer, a layer of a negative differential resistance (NDR) material disposed above the conductive layer, a layer M | 04-25-2013 |
20130099872 | CHAOTIC OSCILLATOR-BASED RANDOM NUMBER GENERATION - Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance. | 04-25-2013 |
20130106480 | METAL-INSULATOR TRANSITION LATCH | 05-02-2013 |
20130106930 | PRINTHEAD ASSEMBLY INCLUDING MEMORY ELEMENTS | 05-02-2013 |
20130176766 | STATEFUL NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state. | 07-11-2013 |
20130207069 | METAL-INSULATOR TRANSITION SWITCHING DEVICES - A metal-insulator transition switching device includes a first electrode and a second electrode. A channel region which includes a bulk metal-insulator transition material separates the first electrode and the second electrode. A method for forming a metal-insulator transition switching device includes depositing a layer of bulk metal-insulator transition material in between a first electrode and a second electrode to form a channel region and forming a gate electrode operatively connected to the channel region. | 08-15-2013 |
20130235651 | METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE - A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed. | 09-12-2013 |
20130249879 | Display Matrix with Resistance Switches - A display matrix may have a resistance switch and a display element formed on a common display substrate. The resistance switch may have a metal insulator transition (MIT) material that has a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance. | 09-26-2013 |
20140003139 | MEMORY DEVICES WITH IN-BIT CURRENT LIMITERS | 01-02-2014 |
20140027700 | MEMRISTOR WITH EMBEDDED SWITCHING LAYER - A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column. | 01-30-2014 |
20140029328 | Storing Data in a Non-volatile Latch - Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair. | 01-30-2014 |
20140035614 | LOGIC CIRCUITS USING NEURISTORS - Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input. | 02-06-2014 |
20140126309 | SHIFTABLE MEMORY - A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset. | 05-08-2014 |
20140211534 | LOCALLY ACTIVE MEMRISTIVE DEVICE - A method to operate an integrated circuit includes operating a locally active memristive device in a locally reactive region of an operating domain where the device exhibits inductor-like behavior, such as a phase shift where a voltage across the device leads a current through the device. | 07-31-2014 |
20140214738 | NEURISTOR-BASED RESERVOIR COMPUTING DEVICES - A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided. | 07-31-2014 |
20140215143 | CROSSBAR MEMORY TO PROVIDE CONTENT ADDRESSABLE FUNCTIONALITY - Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar. | 07-31-2014 |
20140304467 | SHIFTABLE MEMORY EMPLOYING RING REGISTERS - Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted. | 10-09-2014 |
20140313818 | METAL-INSULATOR PHASE TRANSITION FLIP-FLOP - A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device. | 10-23-2014 |
20140359209 | WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM) - Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell. | 12-04-2014 |
20150053909 | NONLINEAR MEMRISTORS - A nonlinear memristor includes a bottom electrode, a top electrode, and an insulator layer between the bottom electrode and the top electrode. The insulator layer comprises a metal oxide. The nonlinear memristor further includes a switching channel within the insulator layer, extending from the bottom electrode toward the top electrode, and a nano-cap layer of a metal-insulator-transition material between the switching channel and the top electrode. The top electrode comprises the same metal as the metal in the metal-insulator-transition material. | 02-26-2015 |
20150194203 | STORING MEMORY WITH NEGATIVE DIFFERENTIAL RESISTANCE MATERIAL - A memory cell includes a transistor with a first source/drain terminal spaced apart from a second source/drain terminal with a semiconductor material; a gate terminal located proximate the semiconductor material such that an increase in a gate terminal voltage increases a conductivity of the semiconductor material; and the first source/drain terminal being connected in series to a negative differential resistance material. | 07-09-2015 |
20150379395 | NEURISTOR-BASED RESERVOIR COMPUTING DEVICES - A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided. | 12-31-2015 |
20150380464 | MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes. | 12-31-2015 |
Patent application number | Description | Published |
20080228972 | Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses - Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services. | 09-18-2008 |
20090059818 | Systems and methods for providing configurable caller id iformation - Systems and methods for providing voice communications using a computing system associated with a first user are disclosed. A communications service is provided that manages packetized voice communications between a plurality of users including the first user. A voice communications configuration software application executing on the first computing system configures a caller ID information associated with a voice communication initiated by the first user. The voice communications configuration software application controllably provides outbound caller ID information for the voice communication. | 03-05-2009 |
20100157852 | Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same - Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services. | 06-24-2010 |
20100208727 | Systems and methods for generating power in a communications system - Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router or switch functions. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. In particular, systems and methods for generating required telephony voltages directly on station cards, rather than on the basis of a large, central ringing or other power supply that supply such telephony voltages to each of the station cards, are disclosed. In accordance with the present invention, a plurality of station cards are provided in the telephony or communications system. One or more DC power supplies provide a source of DC voltage, such as 12 volts, to each of the station cards. The station cards are coupled to a processor of the system. The station cards may support a plurality of analog and/or digital telephony devices, such as telephones facsimile, voice mail, recording, speakerphone, conferencing or other type telephony devices. | 08-19-2010 |
20110078296 | Systems and methods for improved multisite management and reporting of converged communication systems and computer systems - The present invention discloses improved systems and methods for multisite management of computer server systems and in particular converged communication systems based on a decentralized architecture. Certain and various aspects relating to atomic error handling, transaction-based authentication/security, intelligent bandwidth management, decoupled data/configuration messaging, improved scalability, auto-detection functions, business metrics, etc., also are disclosed. A console is disclosed that communicates with each of a plurality of converged communications systems, e.g., preferably through the use of sockets. The actual traffic load is decentralized among the computer server systems, as each one uses direct connections (e.g., via an enhanced file transfer protocol) to access update/configuration data as needed. In addition, an improved communication protocol is disclosed that is optimized for the multisite management architecture of the present invention. An improved set of graphical user interface (GUI) features are described that improve the efficiency of the management of multiple systems. | 03-31-2011 |
20110264782 | Systems and methods for improved multisite management of converged communication systems and computer systems - The present invention discloses improved systems and methods for multisite management of computer server systems and in particular converged communication systems based on a decentralized architecture. Certain and various aspects relating to atomic error handling, transaction-based authentication/security, intelligent bandwidth management, decoupled data/configuration messaging, improved scalability, auto-detection functions, business metrics, etc., also are disclosed. A console is disclosed that communicates with each of a plurality of converged communications systems, e.g., preferably through the use of sockets. The actual traffic load is decentralized among the computer server systems, as each one uses direct connections (e.g., via an enhanced file transfer protocol) to access update/configuration data as needed. In addition, an improved communication protocol is disclosed that is optimized for the multisite management architecture of the present invention. An improved set of graphical user interface (GUI) features are described that improve the efficiency of the management of multiple systems. | 10-27-2011 |
20120249723 | Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same - A system for managing voice and data communications for at least one user is coupled to at least one wide area telecommunications network and includes at least a processor and data storage resources. A first bus is adapted to couple video data between the system and a video unit coupled to the system under control of the processor. A second bus is adapted to couple audio data between the system and a microphone unit coupled to the system under control of the processor, and audio data are coupled to a TDM bus in the system operating under control of the processor. A digital transmission link of the wide area telecommunications network couples the video and audio data from the system, under control of the processor. A user participates in a video call with the video data, while concurrently the user participates in a telephone call with the audio data. Voice communications of the telephone call that stay in a circuit-switched form are provided via the TDM bus, and the video call and the telephone call can provide a conference call. | 10-04-2012 |
20130064240 | Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses - In a communications system, a first packet network is provided. Packetized data is transferred between the system and one or more packet-based devices. A TDM network is provided, and data is transmitted in frames having slots. Data transmitted via the TDM network includes data for voice communications for telephony devices. The TDM network is selectively coupled to the first packet network and a WAN. A processor and a control bus interface circuit control transfer of packetized data and transmittal of data for voice communications. The processor controls processing of packetized data and data'for voice communications. A switch/multiplexer selectively controls providing data to/from particular slots. The processor selectively controls voice communications from telephony devices over the TDM network and packet-based communications over the packet network. Voice communications that stay in a circuit-switched form occur over the TDM network and the WAN. | 03-14-2013 |
20130138789 | Systems and methods for improved multisite management of converged communication systems and computer systems - The present invention discloses improved systems and methods for multisite management of computer server systems and in particular converged communication systems based on a decentralized architecture. Certain and various aspects relating to atomic error handling, transaction-based authentication/security, intelligent bandwidth management, decoupled data/configuration messaging, improved scalability, auto-detection functions, business metrics, etc., also are disclosed. A console is disclosed that communicates with each of a plurality of converged communications systems, e.g., preferably through the use of sockets. The actual traffic load is decentralized among the computer server systems, as each one uses direct connections (e.g., via an enhanced file transfer protocol) to access update/configuration data as needed. In addition, an improved communication protocol is disclosed that is optimized for the multisite management architecture of the present invention. An improved set of graphical user interface (GUI) features are described that improve the efficiency of the management of multiple systems. | 05-30-2013 |
20140189084 | SYSTEMS AND METHODS FOR IMPROVED MULTISITE MANAGEMENT AND REPORTING OF CONVERGED COMMUNICATION SYSTEMS AND COMPUTER SYSTEMS - The present invention discloses improved systems and methods for multisite management of computer server systems and in particular converged communication systems based on a decentralized architecture. Certain and various aspects relating to atomic error handling, transaction-based authentication/security, intelligent bandwidth management, decoupled data/configuration messaging, improved scalability, auto-detection functions, business metrics, etc., also are disclosed. A console is disclosed that communicates with each of a plurality of converged communications systems, e.g., preferably through the use of sockets. The actual traffic load is decentralized among the computer server systems, as each one uses direct connections (e.g., via an enhanced file transfer protocol) to access update/configuration data as needed. In addition, an improved communication protocol is disclosed that is optimized for the multisite management architecture of the present invention. An improved set of graphical user interface (GUI) features are described that improve the efficiency of the management of multiple systems. | 07-03-2014 |