Patent application number | Description | Published |
20080253294 | Data link fault tolerance - A method is provided for automatically generating code to define and control a system of connected hardware elements. The method comprises: accepting a system configuration macro with sub-macros for system elements, subsystem elements, and connections there between; accepting a plurality of tables with a plurality of system element behaviors, a plurality of subsystem element behaviors, and a plurality of connection options; defining the system of connected elements in response to selecting sub-macros; defining the physical links between the system elements and the behavior of the system and subsystem elements in response to populating the selected sub-macro parameters; expanding the selected sub-macros; generating executable code; and, accessing the tables in response to parameters in the executable code. Advantageously, the form and function of the system can be defined with programming, or writing application specific code. | 10-16-2008 |
20080256455 | Method for Defining the Physical Configuration of a Communication System - A method is provided for automatically generating code to define and control a system of connected hardware elements. The method comprises: accepting a system configuration macro with sub-macros for system elements, subsystem elements, and connections there between; accepting a plurality of tables with a plurality of system element behaviors, a plurality of subsystem element behaviors, and a plurality of connection options; defining the system of connected elements in response to selecting sub-macros; defining the physical links between the system elements and the behavior of the system and subsystem elements in response to populating the selected sub-macro parameters; expanding the selected sub-macros; generating executable code; and, accessing the tables in response to parameters in the executable code. Advantageously, the form and function of the system can be defined with programming, or writing application specific code. | 10-16-2008 |
20090092213 | Frequency Hold Mechanism in a Clock and Data Recovery Device - A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency. | 04-09-2009 |
20090147901 | Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device - A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired. | 06-11-2009 |
20090190707 | Frequency Ratio Detection - A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. The reference signal cycles are counted, creating a first binary count. Likewise, the PLL output signal cycles are counted, creating a second binary count. The second binary count is sampled at an interval responsive to the first binary count, and a right-shifted second binary count is supplied as a ratio of the second frequency divided by the first frequency. More explicitly, the sampling is performed when a first binary count sampling threshold of 2 | 07-30-2009 |
20090296857 | Frequency lock detection - A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data signaling frequency to a synthesized signal frequency. In response to the comparing, a difference signal pulse is generated. More explicitly, the difference signal is generated at a rate responsive to the difference between the input data signaling frequency and the synthesized signal frequency. The method counts synthesized signal pulses occurring simultaneously with the difference signal pulse. If the counted synthesized signal pulses exceed a threshold (before the disappearance of the difference signal pulse), it is determined that the input data signaling frequency is about equal to the synthesized signal frequency, and a lock signal is generated. | 12-03-2009 |
20140253228 | INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION - An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block. | 09-11-2014 |
20140266357 | Measure-Based Delay Circuit - A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly. | 09-18-2014 |