Patent application number | Description | Published |
20080213959 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield - An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced. | 09-04-2008 |
20090032814 | SiGe DIAC ESD protection structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 02-05-2009 |
20090038142 | METHODS OF FORMING INDUCTORS ON INTEGRATED CIRCUITS - The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the forming of a metal seed layer, the deposition and patterning of photoresist, the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements. | 02-12-2009 |
20090040000 | INTEGRATED CIRCUITS WITH INDUCTORS - The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes. | 02-12-2009 |
20090091414 | On-chip inductor for high current applications - Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications. | 04-09-2009 |
20090096548 | Tuning and compensation technique for semiconductor bulk resonators - One or more pn junctions are provided on the resonating bar of a semiconductor bulk resonator. When a reverse bias is imposed upon the pn junction(s), a variable depletion layer results and, hence, capacitance. The depletion layer capacitance allows for variable coupling to the resonator bar. The variable coupling allows control circuitry to null out or compensate for variation related to temperature and/or drift. | 04-16-2009 |
20090116269 | Power supply with reduced power consumption when a load is disconnected from the power supply - Detection and control circuitry are added to a conventional power supply to detect when a load, such as a portable electronic device, has been disconnected from the power supply and, when disconnected, interrupt a current path to the primary windings of a transformer within the power supply to substantially reduce the amount of reactive power that is consumed by the power supply. | 05-07-2009 |
20090144035 | Black box model for large signal transient integrated circuit simulation - A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis. | 06-04-2009 |
20090160592 | Helical core on-chip power inductor - An on-chip inductor structure includes a conductive inductor coil and a helical ferromagnetic inductor core that is formed to wrap around the conductive coil. The coil is space-apart from the ferromagnetic core by intervening dielectric material. The helical core structure includes at least one magnetic gap lithographically formed in the core. | 06-25-2009 |
20090162978 | Method of Forming a SiGe DIAC ESD Protection Structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 06-25-2009 |
20090256687 | MAGNETIC FIELD GUARD RINGS - A magnetic guard ring is provided to reduce the susceptibility of a transformer-based data transmission to an externally generated magnetic field. The guard ring structure comprises strategically placed pieces of ferrite material, such as NiFe, that surround the transformer and “steer” the external magnetic field away from the transformer. | 10-15-2009 |
20090296493 | MID-SIZE NVM CELL AND ARRAY UTILIZING GATED DIODE FOR LOW CURRENT PROGRAMMING - A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided. | 12-03-2009 |
20100001365 | ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP - An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk. | 01-07-2010 |
20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 03-18-2010 |
20100140663 | CMOS Compatable fabrication of power GaN transistors on a <100> silicon substrate - In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor. | 06-10-2010 |
20100141292 | Method and system for measuring film stress in a wafer film - In a MEMS wafer, film stresses are measured by placing an inductor array over or under the wafer and measuring inductance variations across the array to obtain a map defining the amount of bowing of the wafer. | 06-10-2010 |
20100141374 | Transformer with signal immunity to external magnetic fields - In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a | 06-10-2010 |
20100142239 | Fully integrated multi-phase grid-tie inverter - In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase. | 06-10-2010 |
20100144116 | Method of forming high lateral voltage isolation structure involving two separate trench fills - In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench. | 06-10-2010 |
20100215995 | MAGNETIC STATE OF CHARGE SENSOR FOR A BATTERY - A battery includes multiple conductive battery plates and a complex electrolytic material located between the conductive battery plates. The battery also includes a conductive sensor wire located within the complex electrolytic material. The conductive sensor wire may be configured to generate a magnetic field within the complex electrolytic material based on an electrical signal flowing through the conductive sensor wire. The battery may further include a temperature sensor wire within the complex electrolytic material. | 08-26-2010 |
20100295550 | ADAPTIVE ENERGY MANAGEMENT TERMINAL FOR A BATTERY - A battery includes multiple conductive plates and a permeable electrolytic material and an ion membrane located between the conductive plates. The battery also includes at least one wire located within one or more of the permeable electrolytic material and the ion membrane. The at least one wire can be configured to regulate a flow of ions through the ion membrane based on an electrical signal flowing through the at least one wire. The at least one wire could also be configured to generate a magnetic field within the permeable electrolytic material based on another electrical signal flowing through the at least one wire. The battery could further include a temperature sensor wire within the permeable electrolytic material. | 11-25-2010 |
20100295638 | METHOD OF SWITCHING A MAGNETIC MEMS SWITCH - A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators. | 11-25-2010 |
20110007570 | METHOD OF READING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time. | 01-13-2011 |
20110007574 | METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time. | 01-13-2011 |
20110025443 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure. | 02-03-2011 |
20110084607 | Integrated driver system architecture for light emitting diodes (LEDS) - A method includes forming one or more capacitors over a substrate. The method also includes forming a transformer at least partially over the substrate. The transformer is adjacent to at least one of the one or more capacitors. At least a portion of the transformer is formed at a same level over the substrate as the one or more capacitors. The method further includes coupling the one or more capacitors and the transformer to at least one embedded integrated circuit die. The one or more capacitors, the transformer, and the at least one embedded integrated circuit die form at least part of a light emitting diode (LED) driver. | 04-14-2011 |
20110095365 | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device. | 04-28-2011 |
20110118607 | SELF-PROPELLED ROBOTIC DEVICE THAT MOVES THROUGH BODILY AND OTHER PASSAGEWAYS - A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder. | 05-19-2011 |
20110174999 | GALVANIC ISOLATION THAT INCORPORATES A TRANSFORMER WITH AN OPTICAL LINK AND THAT CAN BE INTEGRATED ONTO A SINGLE SEMICONDUCTOR SUBSTRATE - Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow. | 07-21-2011 |
20110250730 | Method of Forming High Capacitance Semiconductor Capacitors with a Single Lithography Step - An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer. | 10-13-2011 |
20110260248 | SOI Wafer and Method of Forming the SOI Wafer with Through the Wafer Contacts and Trench Based Interconnect Structures that Electrically Connect the Through the Wafer Contacts - A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors. | 10-27-2011 |
20110269295 | Method of Forming a Semiconductor Wafer that Provides Galvanic Isolation - A semiconductor wafer that provides galvanic isolation is formed in a very cost efficient manner by attaching a non-conductive wafer to a silicon wafer to form a hybrid wafer, and then simultaneously wet etching a large number of hybrid wafers to form a thin non-conductive wafer that is attached to a thick silicon wafer. After a large number of high-voltage devices have been formed on the thin non-conductive wafer, the thick silicon wafer is thinned or removed so that the hybrid wafer is suitable for packaging. | 11-03-2011 |
20110272780 | METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS - An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil. | 11-10-2011 |
20110279214 | High Frequency Semiconductor Transformer - A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The core can also be formed to have a number of sections where the magnetic flux follows the hard axis through each section of the core. | 11-17-2011 |
20120002377 | GALVANIC ISOLATION TRANSFORMER - An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween. | 01-05-2012 |
20120060587 | Gas Detector that Utilizes an Electric Field to Assist in the Collection and Removal of Gas Molecules - A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules. | 03-15-2012 |
20120091501 | Low triggering voltage DIAC structure - In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node. | 04-19-2012 |
20120104548 | Semiconductor Capacitor with Large Area Plates and a Small Footprint that is Formed with Shadow Masks and Only Two Lithography Steps - A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer. | 05-03-2012 |
20120112296 | Semiconductor Inductor with a Serpentine Shaped Conductive Wire and a Serpentine Shaped Ferromagnetic Core and a Method of Forming the Semiconductor Inductor - The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape. | 05-10-2012 |
20120154956 | Self protected snapback device driven by driver circuitry using high side pull-up avalanche diode - In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices. | 06-21-2012 |
20120161294 | Method of Batch Trimming Circuit Elements - Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit. | 06-28-2012 |
20120175676 | Inductively Coupled Photodetector and Method of Forming an Inductively Coupled Photodetector - A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil. | 07-12-2012 |
20120217610 | Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections - A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding. | 08-30-2012 |
20120228480 | OPTICALLY-CONTROLLED SHUNT CIRCUIT FOR MAXIMIZING PHOTOVOLTAIC PANEL EFFICIENCY - An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode. | 09-13-2012 |
20120261753 | DMOS Transistor with a Slanted Super Junction Drift Structure - A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening. | 10-18-2012 |
20120273881 | DMOS Transistor with a Cavity that Lies Below the Drift Region - A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor. | 11-01-2012 |
20120326260 | PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS - A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal. | 12-27-2012 |
20130001735 | THERMALLY CONDUCTIVE SUBSTRATE FOR GALVANIC ISOLATION - A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure. | 01-03-2013 |
20130015850 | Die-Sized Atomic Magnetometer and Method of Forming the MagnetometerAANM Lindorfer; PhilippAACI San JoseAAST CAAACO USAAGP Lindorfer; Philipp San Jose CA USAANM Hopper; Peter J.AACI San JoseAAST CAAACO USAAGP Hopper; Peter J. San Jose CA USAANM French; WilliamAACI San JoseAAST CAAACO USAAGP French; William San Jose CA USAANM Mawson; PaulAACI Los GatosAAST CAAACO USAAGP Mawson; Paul Los Gatos CA USAANM Hunt; StevenAACI San JoseAAST CAAACO USAAGP Hunt; Steven San Jose CA USAANM Parsa; RoozbehAACI San JoseAAST CAAACO USAAGP Parsa; Roozbeh San Jose CA US - The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics. | 01-17-2013 |
20130037908 | Galvanic Isolation Fuse and Method of Forming the Fuse - The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer. | 02-14-2013 |
20130037909 | Semiconductor Structure with Galvanic Isolation - Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die. | 02-14-2013 |
20130049749 | Semiconductor Fluxgate Magnetometer - A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure. | 02-28-2013 |
20130049916 | SEMICONDUCTOR STRUCTURE WITH GALVANICALLY-ISOLATED SIGNAL AND POWER PATHS - A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die. | 02-28-2013 |
20130062725 | SYSTEM AND METHOD OF GALVANIC ISOLATION IN DIGITAL SIGNAL TRANSFER INTEGRATED CIRCUITS UTILIZING CONDUCTIVITY MODULATION OF SEMICONDUCTOR SUBSTRATE - A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier. | 03-14-2013 |
20130062729 | FORMING A FERROMAGNETIC ALLOY CORE FOR HIGH FREQUENCY MICRO FABRICATED INDUCTORS AND TRANSFORMERS - A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency. | 03-14-2013 |
20130099334 | Z-Axis Semiconductor Fluxgate Magnetometer - A z-axis fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence forms a vertical magnetic core structure, a first wire structure wound around the magnetic core structure, and a second wire structure wound around the magnetic core structure. | 04-25-2013 |
20130130439 | FORMED METALLIC HEAT SINK SUBSTRATE, CIRCUIT SYSTEM, AND FABRICATION METHODS - A thermally conductive substrate for suitable for use as a three dimensional heat sink for electrical device systems. The substrate comprises a base element with a cavity comprising a recessed device mounting site. Associated device systems include one or more devices arranged in the three dimensional heat sink which can be encapsulated into a device package and associated construction methodologies. | 05-23-2013 |
20130141089 | Semiconductor GMI Magnetometer - A giant magneto-impedance (GMI) magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the GMI magnetometer. The semiconductor wafer fabrication sequence forms a magnetic conductor, a non-magnetic conductor that is wrapped around the magnetic conductor as a coil, and non-magnetic conductors that touch the opposite ends of the magnetic conductor. | 06-06-2013 |
20130147472 | Micro-Fabricated Atomic Magnetometer and Method of Forming the Magnetometer - The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity. | 06-13-2013 |
20130168808 | MEMS POWER INDUCTOR WITH MAGNETIC LAMINATIONS FORMED IN A CRACK RESISTANT HIGH ASPECT RATIO STRUCTURE - Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants. | 07-04-2013 |
20130176703 | Thermally-Insulated Micro-Fabricated Atomic Clock Structure and Method of Forming the Atomic Clock Structure - A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell. | 07-11-2013 |
20130224887 | Method of Forming a Laminated Magnetic Core with Sputter Deposited and Electroplated Layers - A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process. | 08-29-2013 |
20150027908 | MULTIPLE-CAVITY VAPOR CELL STRUCTURE FOR MICRO-FABRICATED ATOMIC CLOCKS, MAGNETOMETERS, AND OTHER DEVICES - An apparatus includes a vapor cell having multiple cavities fluidly connected by one or more channels. At least one of the cavities is configured to receive a first material able to dissociate into one or more gases that are contained within the vapor cell. At least one of the cavities is configured to receive a second material able to absorb at least a portion of the one or more gases. The vapor cell could include a first cavity configured to receive the first material and a second cavity fluidly connected to the first cavity by at least one first channel, where the second cavity is configured to receive the gas(es). The vapor cell could also include a third cavity fluidly connected to at least one of the first and second cavities by at least one second channel, where the third cavity is configured to receive the second material. | 01-29-2015 |
20150028866 | VAPOR CELL STRUCTURE HAVING CAVITIES CONNECTED BY CHANNELS FOR MICRO-FABRICATED ATOMIC CLOCKS, MAGNETOMETERS, AND OTHER DEVICES - A first apparatus includes a vapor cell having first and second cavities fluidly connected by multiple channels. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity. A second apparatus includes a vapor cell having a first wafer with first and second cavities and a second wafer with one or more channels fluidly connecting the cavities. The first cavity is configured to receive a material able to dissociate into one or more gases that are contained within the vapor cell. The second cavity is configured to receive the one or more gases. The vapor cell is configured to allow radiation to pass through the second cavity. | 01-29-2015 |