Patent application number | Description | Published |
20110305165 | METHOD AND SYSTEM FOR PHYSICAL-LAYER HANDSHAKING FOR TIMING ROLE TRANSITION - Aspects of a method and system for physical-layer handshaking for timing role transition are provided. Prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more PCS code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device. The IDLE symbol(s) may be generated utilizing a second set of one or more PCS code-groups. The first set of PCS code-group(s) may be mutually exclusive with the second set of PCS code-group(s). In response to detecting a received Ethernet physical layer symbol corresponding to the second set of PCS code-groups, the second Ethernet device may make a determination to change its timing role. | 12-15-2011 |
20110305173 | PHASE AND FREQUENCY RE-LOCK IN SYNCHRONOUS ETHERNET DEVICES - A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link. | 12-15-2011 |
20110305248 | CLOCK SELECTION FOR SYNCHRONOUS ETHERNET - An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value. | 12-15-2011 |
20120063296 | Systems and Methods for Providing a Dual-Master Mode in a Synchronous Ethernet Environment - Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process. | 03-15-2012 |
20140043954 | SYSTEMS AND METHODS FOR IMPLEMENTING ENERGY-EFFICIENT ETHERNET COMMUNICATIONS - Systems and methods for implementing an Energy-Efficient Ethernet (EEE) communication are provided. In some aspects, a method includes identifying an EEE signal configured to be communicated via a first set of wires. The method also includes processing the EEE signal such that the processed EEE signal is configured to be communicated via a second set of wires. The second set of wires including fewer wires than the first set of wires. The method also includes communicating the processed EEE signal via the second set of wires. | 02-13-2014 |
20140044133 | SYSTEMS AND METHODS FOR IMPLEMENTING BI-DIRECTIONAL SYNCHRONIZATION PROPAGATION - Systems and methods for implementing bi-directional synchronization propagation between first and second communication devices are provided. The devices are arranged in a loop-timing configuration. A method includes detecting, by the second communication device, a switching signal comprising an indication to switch a timing role of the second communication device and engaging, by the second communication device, in a synchronization handshake with the first communication device over a communication link based on the detection of the switching signal. Engaging in the synchronization handshake includes determining whether the first communication device is configured to support bi-directional synchronization propagation. The method includes switching the timing role of the second communication device based on the synchronization handshake. | 02-13-2014 |
20140079101 | METHOD AND SYSTEM FOR UNCONSTRAINED FREQUENCY DOMAIN ADAPTIVE FILTERING - Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients. | 03-20-2014 |
20140112376 | REDUCED PAIR ETHERNET TRANSMISSION SYSTEM - A system for reduced pair Ethernet transmission. The system includes an interleaver that is operable to receive sets of four code symbols from a physical channel sub-layer (PCS) encoder, wherein each code symbol of each set of four code symbols is associated with one of four channels, and interleave the sets of four code symbols to generate a plurality of interleaved code symbols. The system further includes a serializer that is operable to serialize the plurality of interleaved code symbols to generate a plurality of interleaved and serialized code symbols. The system further includes a transmitter that is operable to transmit the plurality of interleaved and serialized code symbols over an Ethernet medium comprising a single twisted pair of wires. | 04-24-2014 |