Patent application number | Description | Published |
20130127617 | APPARATUS AND METHOD FOR DETECTING UNAUTHORIZED REMOVAL OF ASSET TRACKING DEVICE - An asset tracking device includes a mounting bracket and a housing attached to the mounting bracket. The mounting bracket includes a magnetic portion, first apertures that receive first fasteners for attaching the mounting bracket to the asset, and second apertures that receive second fasteners. Third apertures in the housing, aligned with the second apertures in the mounting bracket, receive the second fasteners for attaching the housing to the mounting bracket. When the housing is attached to the mounting bracket, the housing makes the fasteners in the mounting bracket inaccessible so that the mounting bracket cannot be removed from the asset. When the housing is removed from the mounting bracket, a magnetic switch changes state and triggers a controller to generate a tamper alert with location information indicating the location of the tracking device. A wireless transmitter wirelessly transmits the tamper alert and location information to a central monitoring station. | 05-23-2013 |
20130147617 | SYSTEM FOR COMMUNICATING BETWEEN A TRAILER TRACKING DEVICE, A TRUCK TRACKING DEVICE, AND A CENTRAL MONITORING STATION - When a cargo trailer is coupled to a truck, a trailer tracking device on the trailer acquires an identifier of a truck tracking device attached to the truck. The trailer tracking device then transmits a message to a central server indicating that the trailer is coupled to the truck, which message includes the identifiers of the two tracking devices. The central server associates the identifiers of the two tracking devices in a database. When the trailer is decoupled from the truck, the trailer tracking device transmits a message to the central server indicating that the trailer is decoupled. The trailer tracking device then goes into a sleep mode until the trailer is again coupled to a truck, a predetermined time interval expires, a motion sensor indicates trailer movement, location coordinates indicate a geofence violation, or a low battery voltage condition occurs. Upon any of these events, the trailer tracking device wakes up and transmits to the central server a message indicating which situation caused the transmission and including the location coordinates of the trailer. | 06-13-2013 |
20160049014 | METHOD AND SYSTEM FOR GEOFENCING OF VEHICLE IMPOUND YARDS - A method and system for geofencing of vehicle impound yards. One or more geofences around impound yards are selected. The one or more geofences are associated with one or more vehicles. When a vehicle enters the geofenced area, a user (e.g., an individual, car dealer, finance company, etc.) is immediately notified to prevent excessive impound financial charges. If a vehicle is left in a geofence area, a cumulative time duration and a cumulative finance charge are accurately recorded to reduce or prevent financial fraud. | 02-18-2016 |
Patent application number | Description | Published |
20120262828 | CLAMP BASED ESD PROTECTION CIRCUITS - An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected. | 10-18-2012 |
20120313173 | METHOD FOR ISOLATING RF FUNCTIONAL BLOCKS ON SILICON-ON-INSULATOR (SOI) SUBSTRATES - Buried implants are used to reduce RF (radio-frequency) coupling in a SOI (Silicon-on-insulator) circuit. These buried implants are located above and/or below the BOX (buried oxide) layer of the SOI circuit. These buried implants may completely enclose the PWELL (P-type well) of an NFET (N-type Field Effect Transistor). | 12-13-2012 |
20130286518 | ELECTRO-STATIC DISCHARGE POWER SUPPLY CLAMP WITH DISABLEMENT LATCH - The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail. | 10-31-2013 |
20130286519 | ELECTRO-STATIC DISCHARGE POWER SUPPLY CLAMP WITH DISABLEMENT LATCH - The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail. | 10-31-2013 |
20140091858 | LOCAL VOLTAGE CONTROL FOR ISOLATED TRANSISTOR ARRAYS - Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor. | 04-03-2014 |
20140347121 | LOCAL VOLTAGE CONTROL FOR ISOLATED TRANSISTOR ARRAYS - Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor. | 11-27-2014 |
20150325568 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT - Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time. | 11-12-2015 |
20160043542 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time. | 02-11-2016 |
Patent application number | Description | Published |
20120236857 | MULTICAST ADDRESS LEARNING IN AN INPUT/OUTPUT ADAPTER OF A NETWORK PROCESSOR - An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included. | 09-20-2012 |
20140254593 | NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL - An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine. | 09-11-2014 |
20150331718 | NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL - An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine. | 11-19-2015 |