Patent application number | Description | Published |
20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
20080256319 | Memory controller - A memory controller includes a page configure module that communicates with a memory array comprising B memory blocks each including P pages. The page configure module selectively configures memory cells in the P pages of each of the B memory blocks to store from 1 to T bits per cell. The page configure module also generates a memory map based on the configuration. B, P, and T are integers greater than 1. At least one of a write module selectively writes data to the memory array based on the memory map or a read module selectively reads data from the memory array based on the memory map. | 10-16-2008 |
20080291741 | BIT LINE DECODER ARCHITECTURE FOR NOR-TYPE MEMORY ARRAY - A bit line decoder for sensing states of memory cells of a memory array includes control devices and a control module. The control devices selectively communicate with bit lines. The control devices are arranged in a multi-level configuration having a plurality of levels, each level having a plurality of the control devices. The control module selects from the bit lines a first bit line and a second bit line associated with a memory cell located in the memory array when determining a state of the memory cell. The control module generates first control signals that deselect one or more of the control devices at each level. When one or more control devices at each level are deselected, a first group of the bit lines including the first bit line is charged to a first potential, and a second group of the bit lines including the second bit line is charged to a second potential. | 11-27-2008 |
20080298140 | MEMORY STRUCTURE WITH WORD LINE BUFFERS - A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module. | 12-04-2008 |
20090010050 | Calibration system for writing and reading multiple states into phase change memory - A memory system includes phase change memory cells. A control module causes one of the phase change memory cells to be written using a write parameter, causes a resistance value of the one of the phase change memory cells to be read back, adjusts the write parameter, and causes the writing, reading and adjusting to be repeated until the resistance value is within a predetermined range of a target resistance value. | 01-08-2009 |
20090010060 | Bit line decoder architecture for nor-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes D control devices and a control module. The D control devices selectively communicate with (D−1) bit lines of the memory array and are arranged in first and second levels of the bit line decoder. (D−2) of the D control devices are arranged in the first level, and two of the D control devices are arranged in the second level. log | 01-08-2009 |
20090010061 | Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder, a control module, and an isolation circuit. The first sub-decoder is adjacent to the memory array and includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selectively communicate with a first set of S of B bit lines of the memory array, where log | 01-08-2009 |
20090010062 | Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders, R isolation circuits, a second sub-decoder, and a sensing circuit. The R first sub-decoders communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. The R isolation circuits each have first ends that communicate with the R first sub-decoders, respectively, and second ends. The second ends of a first of the R isolation circuits communicate with corresponding the second ends of (R- | 01-08-2009 |
20090052256 | THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature. | 02-26-2009 |
20090138654 | FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM - A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings. | 05-28-2009 |
20090196117 | SYSTEM AND METHOD FOR MEMORY ARRAY DECODING - A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M switch module selectively controls access to up to J of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1, and J is an integer greater than or equal to 1 | 08-06-2009 |
20090319825 | MONITORING MEMORY - Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory. | 12-24-2009 |
20100095187 | FILE SERVER FOR REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) SYSTEM - A redundant array of independent disks system includes a first storage array with a first target processing module and a first plurality of storage devices. A second storage array includes a second target processing module and a second plurality of storage devices. A data processing module receives a plurality of data blocks for storage in one or more of the first and second plurality of storage devices. The data processing module assigns a first data block of the plurality of data blocks to the first target processing module and a second data block of the plurality of data blocks to the second target processing module. The first and second target processing modules concurrently generate first and second error checking and correcting data based on the first data block, respectively. | 04-15-2010 |
20100110574 | TESTING STORAGE SYSTEM ELECTRONICS USING LOOPBACK - A system includes a hard disk controller module configured to control a hard disk. A read channel device is in communication with the hard disk controller module via a read bus and a write bus. The read channel device includes a loopback circuit configured to selectively loop back the write bus to the read bus. The read channel is configured to generate a write clock for the hard disk controller module to write data on the write bus. The read channel is configured to generate a read clock for the hard disk controller module to read the data on the read bus. The write clock is independent of the read clock. | 05-06-2010 |
20100157759 | AUTOMATIC WRITE STRATEGY CALIBRATION METHOD FOR OPTICAL DRIVE - An optical media playback device includes a memory to store calibration data specifying how a mark of a particular length should be formed on an optical storage media. A control module writes a training pattern onto the optical storage media based on the calibration data. The training pattern includes a first mark having a first length. A control module reads the training pattern previously written onto the optical storage media and determines whether the first length of the first mark corresponds to the particular length specified by the calibration data. The control module adjusts the calibration data stored in the memory in response to the first length of the first mark not corresponding to the particular length specified by the calibration data. | 06-24-2010 |
20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 07-08-2010 |
20100253286 | POWER MANAGEMENT CIRCUIT FOR RECHARGEABLE BATTERY STACK - A charge-balancing system includes N circuits and a control module, where N is an integer greater than or equal to 1. Each of the N circuits includes first and second switches connected in series and an inductance having a first end connected between the first and second switches. The control module outputs control signals to control the first and second switches. A second end of the inductance of a first one of the N circuits is connected between two cells of a first pair of 2N series-connected cells of a battery stack. The first and second switches of the first one of the N circuits are connected in parallel to the first pair of 2N series-connected cells. | 10-07-2010 |
20100315927 | WRITE SPLICE FOR OPTICAL RECORDING CHANNELS - An enhanced write splice for optical recording channels is disclosed. Optical control circuitry locks to previously-written data and determines the estimated write splice location. A training sequence is written to the optical medium at a location based on the estimated write splice location. The phase offset is then estimated by reading the training sequence. A new write splice location may then be calculated compensating for the phase offset estimate. Finally, the new data to be spliced may be written or overwritten to the channel at the new write splice location. | 12-16-2010 |
20110001547 | THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature. | 01-06-2011 |
20110060969 | METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY - A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels. | 03-10-2011 |
20110115567 | CLOCK TURN-ON STRATEGY FOR POWER MANAGEMENT - A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received. | 05-19-2011 |
20110163728 | POWER MANAGEMENT CIRCUIT OF RECHARGEABLE BATTERY STACK - A system includes a sensing module and a switching module. The sensing module is configured to sense output voltages of first and second cells connected in series in a rechargeable battery stack. The switching module is configured to alternately connect a capacitance across the first cell and the second cell at a switching frequency when a difference in the output voltages is greater than or equal to a first threshold. The switching module is further configured to stop alternately connecting the capacitance when the difference is less than or equal to a second threshold, wherein the first threshold is greater than the second threshold. | 07-07-2011 |
20110205809 | Bit Line Decoder Architecture for NOR-Type Memory Array - An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state of a given memory cell, the bit line decoder (i) precharges a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharges a second bit line of the two corresponding bit lines to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential. | 08-25-2011 |
20110238884 | Memory Controller for Setting Page Length and Memory Cell Density for Semiconductor Memory - A memory controller including a type determining module and a page determining module. The type determining module is configured to determine a type of memory to which the memory controller is connected, wherein the memory includes a memory block comprising a plurality of pages, and each page includes a plurality of memory cells. The page configure module is configured to generate a memory map based on the determined type of the memory. The memory map specifies, for each page, (i) a number of memory cells for storing data, and (ii) a number of memory cells for storing overhead. The number of memory cells for storing data and the number of memory cells for storing overhead in a first page is configurable to be different from the number of memory cells for storing data and the number of memory cells for storing overhead in a second page. | 09-29-2011 |
20110266976 | System and Method of Tuning Current for LEDs - An apparatus includes a LED and a regulator circuit. The regulator circuit controls the current provided to the LED according to a calibration signal that is coupled to the current. The regulator circuit adjusts the output of the LED when the calibration signal is adjusted. In this manner, the LED may be calibrated to generate light at a desired brightness level and color level. | 11-03-2011 |
20110267904 | HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY - A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values. | 11-03-2011 |
20110305095 | System and Method for Memory Array Decoding - A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line. | 12-15-2011 |
20110310672 | Threshold Voltage Digitizer for Array of Programmable Threshold Transistors - A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor. | 12-22-2011 |
20120041992 | File Server for Redundant Array of Independent Disks (RAID) System - A system comprising an interface, a plurality of storage arrays, a data processing module, and a switch module. The interface receives data blocks from a host via a network. The data processing module connected between the interface and the plurality of storage arrays, wherein the data processing module is configured to (i) determine which ones of the data blocks each of a plurality of target processing modules of the storage arrays is to perform error checking and correcting processing, and (ii) transfer each of the data blocks from the interface to a respectively assigned one of the plurality of target processing modules. The switch module provides communication paths between the data processing module and the plurality of storage arrays. | 02-16-2012 |
20120042224 | System and Method for Correcting Errors in Non-Volatile Memory Using Product Codes - A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension. | 02-16-2012 |
20120102245 | UNIFIED I/O ADAPTER - Systems, methods, and other embodiments associated with a unified hybrid input/output adapter are described. According to one embodiment, an apparatus includes an Input/Output (I/O) interconnect configured to connect with a host device and to provide communications with the host device. The apparatus also includes a network adapter connected to the I/O interconnect and configured to communicate with a network storage. The apparatus includes a host adapter connected to the I/O interconnect and configured to communicate with a first storage device and a second storage device. The first storage device has a higher latency than the second storage device. The apparatus further includes a storage logic configured to control the I/O interconnect to cause storage access requests from the host device to be cached in the second storage device via the host adapter. | 04-26-2012 |
20120147495 | METHOD AND APPARATUS FOR REDUCING REPEATABLE RUNOUT IN STORAGE SYSTEMS - A storage system includes a first buffer configured to store a first repeatable runout profile (RRP) for a sector of a rotating storage medium. A second buffer is configured to store a second RRP for the sector. A controller: controls a servo of the rotating storage medium based on the first RRP during a first revolution of the rotating storage medium; and learns the second RRP (i) while operating in a track-following mode, and (ii) during the first revolution. The controller ceases learning of the second RRP when one of (i) the controller is operating in a seek mode and (ii) the rotating storage medium is in an off-track state. Subsequent to the first revolution of the rotating storage medium and based on whether the learning of the second RRP was stopped during the first revolution, the controller replaces the first RRP with the second RRP in the first buffer. | 06-14-2012 |
20120176846 | Threshold Voltage Digitizer for Array of Programmable Threshold Transistors - A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor. | 07-12-2012 |
20120262994 | SYSTEM AND METHOD FOR MEMORY ARRAY DECODING - A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line. | 10-18-2012 |
20120278545 | NON-VOLATILE MEMORY DEVICE WITH NON-EVENLY DISTRIBUTABLE DATA ACCESS - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes memory cells arranged among physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 11-01-2012 |
20120319621 | TRIAC DIMMING SYSTEMS FOR SOLID-STATE LOADS - A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage. | 12-20-2012 |
20130020956 | CORRELATED COLOR TEMPERATURE CONTROL METHODS AND DEVICES - New and useful methods and systems for providing lighting control are disclosed. For example, in an embodiment a lighting system includes one or more first solid state lights having a first aesthetic color, one or more second solid state lights having a second aesthetic color, the second aesthetic color having an appreciably longer wavelength than the first aesthetic color, and an amplitude correlation circuit configured to control a ratio of first light produced by the one or more first solid state lights to second light produced by the one or more second solid state lights as a function of a received dimming control signal. | 01-24-2013 |
20130057163 | REGULATOR FOR LED LIGHTING COLOR MIXING - A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential. | 03-07-2013 |
20130067286 | CACHING SYSTEM WITH REMOVABLE MEMORY CARD - Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria. | 03-14-2013 |
20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 03-28-2013 |
20130127550 | FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION - A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers. | 05-23-2013 |
20130132799 | PROVIDING LOW-LATENCY ERROR CORRECTING CODE CAPABILITY FOR MEMORY - A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length. | 05-23-2013 |
20130147423 | METHOD AND APPARATUS FOR POWER SWITCHING - Aspects of the disclosure provide a circuit. The circuit includes a switch and a switch controller. The switch is between a first node that receives a first power supply and a second node, and is controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node. The switch controller is configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply. | 06-13-2013 |
20130162156 | METHOD AND APPARATUS FOR CURRENT CONTROL WITH LED DRIVER - Aspects of the disclosure provide a circuit that includes a detection circuit and a controller. The detection circuit is configured to detect a starting of a conduction in a power supply provided via an electronic transformer. The controller is configured to control a current regulating circuit to pull a current from the electronic transformer at a pre-determined level during a time duration following the starting of the conduction, and pull the current at a reduced level according to a pre-determined profile after the time duration. | 06-27-2013 |
20130235638 | HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY - A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller. | 09-12-2013 |
20130286749 | System and Method for Memory Array Decoding - A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines. | 10-31-2013 |
20130290813 | Method and System For Error Correction in Flash Memory - A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal. | 10-31-2013 |
20130300344 | Power Management Circuit For Rechargeable Battery Stack - A system including a first cell, a second cell, a first switch, a second switch, an inductance, and a control module. The first cell and the second cell are connected in series to each other and respectively output a first voltage and a second voltage. The first switch and the second switch are connected in series to each other and are connected across the first cell and the second cell. The inductance is connected between the first switch and the second switch, and between the first cell and the second cell. The control module generates control signals to control the first switch and the second switch, and to transfer charge between the first cell and the second cell via the inductance until a difference between the first voltage and the second voltage is less than or equal to a predetermined threshold. The predetermined threshold is not equal to zero. | 11-14-2013 |
20130305122 | APPARATUS AND METHOD FOR STORING AND ASSIGNING ERROR CHECKING AND CORRECTING PROCESSING OF DATA TO STORAGE ARRAYS - A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks of data received by the first interface. A processor (i) determines error checking and correcting processing to be applied to each block of data of the blocks of data, and (ii) for each block of data, (a) transfers the block of data from the memory to a selected storage array of the storage arrays, and (b) assigns, to the selected storage array, the error checking and correcting processing to be applied to the block of data. The memory stores a map. The map indicates storage of the blocks of data among the storage arrays. | 11-14-2013 |
20130307434 | METHOD AND APPARATUS FOR CONTROLLING A LIGHTING DEVICE - Aspects of the disclosure provide a method. The method includes detecting a dimming characteristic in an energy source that provides energy to be transferred to a load via a magnetic component, receiving a dimming control signal, and controlling a switch in connection with the magnetic component based on the dimming characteristic and the dimming control signal to transfer energy to the load via the magnetic component. | 11-21-2013 |
20130322182 | THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A calibration module generates a plurality of calibration codes respectively for a first plurality of transistors located along (i) a plurality of bit lines and (ii) a first word line of a memory array. Each of the calibration codes is based on a distance of a corresponding one of the plurality of bit lines from an input of the first word line. A voltage generator outputs a first voltage generated based on a first plurality of codewords to an input of a second word line. A control module determines values of threshold voltages of a second plurality of transistors located along (i) the plurality of bit lines and (ii) the second word line based on (a) the first plurality of codewords and (b) currents sensed through the second plurality of transistors, and adjusts the values of the threshold voltages based on the calibration codes. | 12-05-2013 |
20140002005 | Power Management Circuit of Rechargeable Battery Stack | 01-02-2014 |
20140082492 | MODIFIABLE CONTEXTUAL HELP CONTENT PROVIDED IN-LINE WITHIN AN APPLICATION - Systems, methods, and other embodiments associated with providing contextual content along with elements within an application are described. According to one embodiment, an apparatus includes icon logic configured to generate, in response to detecting a selection of a page element, an icon that indicates whether contextual content associated with the page element is available. The page element is a display element of a graphical user interface (GUI) for an application. The apparatus includes context logic configured to generate a context panel in response to detecting an input associated with the icon. The context logic is configured to generate the context panel with a first tab and a second tab. The first tab includes a description of the page element and the second tab includes a set of comments from users about the page element. | 03-20-2014 |
20140104924 | APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS - A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch. | 04-17-2014 |
20140104926 | SYSTEMS AND METHODS FOR READING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS - A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell. | 04-17-2014 |
20140104927 | CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS - A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction. | 04-17-2014 |
20140104928 | METHOD AND APPARATUS FOR FORMING A CONTACT IN A CELL OF A RESISTIVE RANDOM ACCESS MEMORY TO REDUCE A VOLTAGE REQUIRED TO PROGRAM THE CELL - A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area. | 04-17-2014 |
20140112057 | APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS - A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell. | 04-24-2014 |
20140170832 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS - A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory. | 06-19-2014 |
20140173197 | METHOD AND STORAGE DRIVE FOR WRITING PORTIONS OF BLOCKS OF DATA IN RESPECTIVE ARRAYS OF MEMORY CELLS OF CORRESPONDING INTEGRATED CIRCUITS - A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells. | 06-19-2014 |
20140201600 | APPARATUS AND METHOD FOR ENCODING DATA FOR STORAGE IN MULTI-LEVEL NONVOLATILE MEMORY - A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory. | 07-17-2014 |
20140204682 | METHOD AND APPARATUS FOR SIMULTANEOUSLY ACCESSING A PLURALITY OF MEMORY CELLS IN A MEMORY ARRAY TO PERFORM A READ OPERATION AND/OR A WRITE OPERATION - A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell. | 07-24-2014 |
20140325179 | SYSTEM AND METHOD FOR WRITING PILOT DATA INTERSPERSED WITH USER DATA FOR ESTIMATING DISTURBANCE EXPERIENCED BY USER DATA - A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page. | 10-30-2014 |
20140327372 | METHOD AND APPARATUS FOR DIMMABLE LED DRIVER - Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source. | 11-06-2014 |
20140333216 | MULTI-STRING DIMMABLE LED DRIVER - An apparatus includes a first LED driver configured to control a first string of LEDs, a second LED driver configured to control a second string of LEDs, a third LED driver configured to control a third string of LEDs, and a control circuit configured to receive a control signal and to control the first, second, and third LED drivers so that the first, second, and third strings of LEDs cooperate in producing light according to the control signal and a color curve. | 11-13-2014 |
20140347894 | CURRENT SHAPING FOR DIMMABLE LED - Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC. | 11-27-2014 |
20150015158 | APPARATUSES FOR BLEEDING CURRENT FROM A TRANSFORMER OF A SOLID-STATE LIGHT EMITTING DIODE - A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode. | 01-15-2015 |
20150058702 | MULTI-LEVEL MEMORY CONTROLLER WITH PROBABILITY-DISTRIBUTION-BASED ENCODING - A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells. | 02-26-2015 |
20150063004 | METHOD AND APPARATUS FOR REFORMING A MEMORY CELL OF A MEMORY - A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle. | 03-05-2015 |
20150078047 | CURRENT SHAPING FOR DIMMABLE LED - Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC. | 03-19-2015 |