Palus
Alexandre Palus, Sugar Land, TX US
Patent application number | Description | Published |
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20110087932 | Method and System for Detecting a Failure In an Error Correcting Unit - In order to detect a faulty error correcting unit ( | 04-14-2011 |
20120066551 | Run-time Verification of CPU Operation - Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum. | 03-15-2012 |
Alexandre Palus, Houston, TX US
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20100088446 | PRIORITIZING INTERRUPT CONTROLLER - A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports. | 04-08-2010 |
Alexandre Pierre Palus, Sugarland, TX US
Patent application number | Description | Published |
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20120173924 | DUAL ENDIANESS AND OTHER CONFIGURATION SAFETY IN LOCK STEP DUAL-CORE SYSTEM, AND OTHER CIRCUITS, PROCESSES AND SYSTEMS - An electronic circuit includes a microcontroller processor ( | 07-05-2012 |
Alexandre Pierre Palus, Austin, TX US
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20150143181 | DUAL ENDIANESS AND OTHER CONFIGURATION SAFETY IN LOCK STEP DUAL-CORE SYSTEM, AND OTHER CIRCUITS, PROCESSES AND SYSTEMS - An electronic circuit includes a microcontroller processor ( | 05-21-2015 |
Alexandre Pierre Palus, Houston, TX US
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20120185628 | Locking/Unlocking CPUs to Operate in Safety Mode or Performance Mode Without Rebooting - An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate. | 07-19-2012 |
Alexandre Pierre Palus, Sugar Land, TX US
Patent application number | Description | Published |
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20120226949 | Multi-Channel Bus Protection - An embodiment of the invention provides a method for managing errors on a bus. Information read from a source is encoded. The encoded information is transmitted on a channel that is part of the bus. The encoded information is evaluated. When no errors are detected, the decoded information is provided to a target. When the decoded information has an error or errors that can not be corrected, the source is asked to present the information to the bus again. When an error or errors can be corrected, the corrected information is sent to the target. | 09-06-2012 |
Ernest Palus, Montreal CA
Patent application number | Description | Published |
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20090099376 | TIGECYCLINE AND METHODS OF PREPARING INTERMEDIATES - Methods of preparing and purifying 9-nitrominocycline and 9-aminominocycline and salts thereof used in the process of making tigecycline, are disclosed. In one embodiment, the invention is directed to a method of preparing the compound of formula 1 | 04-16-2009 |