Patent application number | Description | Published |
20110001138 | Thin Film Transistor Array and Method for Manufacturing the Same - A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist. | 01-06-2011 |
20110149224 | POLYMER STABILIZATION ALIGNMENT LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY PANEL - The present invention provides a polymer stabilization alignment liquid crystal display panel having a plurality of pixel regions. Each pixel region includes a main region and a sub region, and a first pixel electrode and a second pixel electrode correspond to the main region and the sub region respectively. Each first pixel electrode is separated from the adjacent data line and thereby forming a gap therebetween. Each second pixel electrode partially overlaps the adjacent data line. In addition, each second pixel electrode includes a plurality of branches, and at least one edge of the branches may be parallel to the data lines. Accordingly, the present invention not only can increase the aperture ratio, but also well control the liquid crystal molecules located near the data lines. Therefore, the display quality of the liquid crystal display panel can be improved. | 06-23-2011 |
20110317103 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, pixel regions, pixel electrodes and color filters. Each pixel region at least includes a main pixel region and a sub pixel region. Each pixel electrode is disposed on the first substrate. Each pixel electrode includes a first electrode disposed in the main pixel region and a second electrode disposed in the sub pixel region. Each color filter is disposed between the first substrate and the second substrate and corresponds to each pixel region. Each color filter includes a curved surface facing the liquid crystal layer and an extreme thickness position. When a predetermined voltage is applied to each pixel electrode, aligning directions of the liquid crystal molecules disposed above the first electrode are converged toward a center. The extreme thickness position substantially overlaps the center in a vertical projection direction. | 12-29-2011 |
20130278853 | POLYMER STABILIZATION ALIGNMENT LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY PANEL - The present invention provides a polymer stabilization alignment liquid crystal display panel having a plurality of pixel regions defined by plurals of data lines and gate lines. Each pixel region includes a main region and a sub region, and a first pixel electrode and a second pixel electrode correspond to the main region and the sub region respectively, wherein each of the data lines has a first width adjacent to the main display region and a second width adjacent to the sub display region, and the second width is larger than the first width. Each first pixel electrode is separated from the adjacent data line and thereby forming a gap therebetween. Each second pixel electrode partially overlaps the adjacent data line to form an overlap width. Accordingly, the present invention not only can increase the aperture ratio, but also well control the liquid crystal molecules located near the data lines. | 10-24-2013 |
20140342554 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY - A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist. | 11-20-2014 |
Patent application number | Description | Published |
20090153280 | STRUCTURE OF TRANSFORMER - A transformer includes a first bobbin piece, a second bobbin piece, a first pin, a second pin and a magnetic core assembly. The first bobbin piece has a first channel therein and a covering element, and a primary winding coil is wound on the first bobbin piece. The second bobbin piece includes a first secondary side plate, a second secondary side plate, a plurality of partition plates, a wall portion, and a secondary base, and a secondary winding coil is wound on the second bobbin piece. The second pin includes a wire-arranging part, an insertion part and an intermediate part, wherein the wire-arranging part is protruded from the second secondary side plate, the intermediate part is buried in the wall portion, and the insertion part is protruded from the bottom surface of the secondary base. The magnetic core assembly is partially embedded within said first channel of said first bobbin piece and said second channel of said second bobbin piece. A first terminal of the secondary winding coil is fixed on the first pin and a second terminal of the secondary winding coil is fixed on the wire-arranging part of the second pin. At least parts of the second bobbin piece are received in the covering element of the first bobbin piece, and the covering element has an insulating partition for isolating the magnetic core assembly from the primary winding coil and the secondary winding coil. | 06-18-2009 |
20090278646 | STRUCTURE OF TRANSFORMER - A transformer includes multiple bobbins arranged side by side, a primary winding coil, a secondary winding coil and a magnetic core assembly. Each bobbin includes a main body, multiple partition plates, a primary winding coil, a secondary winding coil and a magnetic core assembly. The main body has at least two sidewalls respectively disposed at two opposite ends thereof. The partition plates are disposed on the main body for respectively cooperating with the sidewalls to define a first winding region and a second winding region. The first winding region and the second winding region are separated by the partitions plates. The spacer is disposed within the channel. The primary winding coil and the secondary winding coil are respectively wound on the first winding portion and the second winding portion of each bobbin. The magnetic core assembly partially embedded into the channels of the bobbins and sustained against the spacer. | 11-12-2009 |
Patent application number | Description | Published |
20110235364 | Panel Display Module and Manufacturing Method Thereof - A panel display module and a manufacture method thereof are disclosed. The panel display includes a backlight module, a display panel, a clear cover, and reinforced glue. The backlight module has a light source module and a frame that positions the light source module and other elements to provide structural protection. The display panel is disposed on the light exiting side of the light source module. The clear cover is disposed on one side of the display panel opposite to the light source module. The reinforced glue is distributed encircling the frame and adheres respectively to the frame and to the portion of the clear cover protruding over the display panel. The reinforced glue has a first side adhering onto the frame and a second side adhering onto the clear cover. | 09-29-2011 |
20120099257 | Display Module - A display module having an improved assembly structure is provided. The display module includes a frame, a display panel, and a glue. The frame has a side wall and a supporting part, wherein the supporting part has a supporting surface and the side wall is formed on the periphery of the supporting surface. A groove is formed on the supporting surface adjacent to the side wall and is distributed along the side wall. The display panel is disposed within the frame and has a bottom face and a side face. The bottom face is supported by the supporting surface of the supporting part. The side face faces the side wall and forms a gap with the side wall. The glue is filled in the gap and adheres the side wall to the side face. | 04-26-2012 |
20140022764 | Display Module - A display module having an improved assembly structure is provided. The display module includes a frame, a display panel, and a glue. The frame has a side wall and a supporting part, wherein the supporting part has a supporting surface and the side wall is formed on the periphery of the supporting surface. A groove is formed on the supporting surface adjacent to the side wall and is distributed along the side wall. The display panel is disposed within the frame and has a bottom face and a side face. The bottom face is supported by the supporting surface of the supporting part. The side face faces the side wall and forms a gap with the side wall. The glue is filled in the gap and adheres the side wall to the side face. | 01-23-2014 |
Patent application number | Description | Published |
20090294943 | Stacked structure of integrated circuits having space elements - A stacked structure of integrated circuits having spacer elements includes a substrate, a spacer element, a lower-layer integrated circuit, an upper-layer integrated circuit, and a molding layer. The substrate includes an upper surface on which the spacer element and the lower-layer integrated circuit are arrayed with each other. The lower-layer integrated circuit includes a solder-pad region and a non-solder-pad region adjacent to the spacer element. The upper-layer integrated circuit is disposed on the spacer element, and covers partly over the non-solder-pad region of the lower-layer integrated circuit. Therefore, the overall height of the stacked structure of integrated circuits can be lowered, making the packaging process simplified, the manufacturing process more stable, and the yield rate of production will be raised. Since the inlet end of the wire is electrically connected to the solder pad of the upper-layer integrated circuit, the height of the packaging can be reduced, and so the whole height of the stacked structure of integrated circuits. | 12-03-2009 |
20100035380 | Method for fabricating package structure of stacked chips - The invention relates to a method for fabricating a package structure of stacked chips, comprising the following steps: firstly, providing a substrate; attaching a first chip and a second chip on the upper surface of the substrate, in which the second chip is stacked on the upper side of the first chip; then connecting a first bonding wire between a second solder pad of the second chip and a first region of a first solder pad of the first chip; and connecting a second bonding wire between a second region of the first solder pad of the first chip and the metal contact of the substrate, whereby the invention is capable of tremendously reducing the volume as a whole, effectively solving the problem of having much bonding wire circuit, and reducing the volume and quantity occupied by the solder pads on the substrate, thereby reducing complexity of the circuit layout on the substrate. | 02-11-2010 |
Patent application number | Description | Published |
20090108111 | Discharge opening and power control structure of a grinder - A discharge opening and power control structure of a grinder is disclosed to include a grinder body, which has a discharge opening for discharge of the ground powder and a battery chamber with a positive and negative contacts extended out of the grinder body, and a shut device, which has a slot and a metal contact plate and is rotatable relative to the grinder body between the open position where the slot is in alignment with the discharge opening to open the discharge opening and the metal contact plate is in contact with the positive and negative contacts to turn on the power supply, and the close position where the discharge opening is closed and the power supply of the grinder is off. | 04-30-2009 |
20100101434 | CUTTING DEVICE FOR BLOCK-SHAPED FOOD - The present invention relates to a cutting device for block-shaped food, comprises a container main body, a tube-shaped cutting mechanism having a grinding plate, an extruding mechanism composed by a screw rod and an extruding sheet, and a sealing cover connected to the top end of the container main body. An accommodating chamber having a polygonal cross section shape provided inside the container main body is served to accommodate block-shaped food; the tube-shaped cutting mechanism is connected to the bottom end of the container main body so the grinding plate thereof is provided adjacent to an opening at the bottom end of the container main body, and the bottom end and the top end of the screw rod are respectively fastened and pivotally connected to the grinding plate and the sealing cover, and the screw rod is screw-fitted with the extruding sheet in the accommodating chamber; when a relative movement is generated between the container main body and the cutting mechanism, the extruding sheet is downwardly moved along the screw rod, so the food is pressed toward the grinding plate and the food is cut to a power, strip or thin-sheet status; when the extruding sheet is upwardly moved along the screw rod and the resilient buckling member is buckled on the buckling flange provided inside the sealing cover, when the sealing cover is separated from the top end of the container main body, the extruding sheet is also separated from the screw rod, so block-shaped food is able to be refilled. | 04-29-2010 |
Patent application number | Description | Published |
20090002264 | DISPLAY APPARATUS AND METHOD FOR DRIVING DISPLAY PANEL THEREOF - A display apparatus and a method for driving a display panel thereof are provided. Each column of data line in the display panel has tow sub-data lines. The driving method is described as follows. An input image signal is divided into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group. An image signal is formed by inserting a reset data in each group of image segments. Display data of a first group are written in K batches according to a first start wave. After a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines. | 01-01-2009 |
20120026141 | Bistable display apparatus and driving method - A bistable display with dot-matrix pixels is disclosed. The bistable display includes a front substrate, a plurality of first conductive electrodes, an electrophoretic medium layer, a plurality of second conductive electrodes, and a back substrate. The plurality of first conductive electrodes is disposed below the front substrate and parallel to each other along a first direction. The electrophoretic medium layer is disposed below the front substrate and the plurality of first conductive electrodes. The plurality of second conductive electrodes is disposed on the back substrate and parallel to each other along a second direction different from the first direction. A pixel is formed at each intersection of each first conductive electrode and each second conductive electrode. | 02-02-2012 |
20120299904 | APPARATUS AND METHOD FOR DRIVING DISPLAY - An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data. | 11-29-2012 |
20140002435 | DATA DRIVER FOR ELECTROPHORETIC DISPLAY | 01-02-2014 |
20140375696 | IMAGE DISPLAY APPARATUS AND BACKLIGHT ADJUSTING METHOD THEREOF - An image display apparatus and a backlight adjusting method are provided. The image display apparatus has a backlight module. The image display apparatus includes an ambient light sensor, an image content analyzer and a backlight controller. The ambient light sensor detects a luminance of ambient light. The image content analyzer receives an image data. The backlight controller sets a backlight basic value according to the luminance of ambient light, and sets a backlight adjusting ratio according to the image data and the luminance of ambient light. The backlight controller further sets a luminance of the backlight module according to the backlight basic value and the backlight adjusting ratio. | 12-25-2014 |
Patent application number | Description | Published |
20100315511 | Image capturing device - An image capturing device includes a lens module, a filter, two sensors, a first image processing module, and a second image processing module. The lens module is adapted to receive the image beam. The filter is adapted to split the image beam into a first beam and a second beam. The two sensors are disposed in transmission paths of the first beam and the second beam separately, and the sensors separately convert the first beam and the second beam into a first optical information and a second optical information. The first image processing module and the second image processing module are disposed in transmission paths of the first optical information and the second optical information separately, and the image processing modules separately convert the optical information into image information. The second image processing module integrates the first image information and the second image information into a color image. | 12-16-2010 |
20140313344 | Image Capturing Method and Image Capturing Device - An image capturing device includes a lens module, a filter, two sensors, a first image processing module, and a second image processing module. The lens module is adapted to receive the image beam. The filter is adapted to split the image beam into a first beam and a second beam. The two sensors are disposed in transmission paths of the first beam and the second beam separately, and the sensors separately convert the first beam and the second beam into a first optical information and a second optical information. The first image processing module and the second image processing module are disposed in transmission paths of the first optical information and the second optical information separately, and the image processing modules separately convert the optical information into image information. The second image processing module integrates the first image information and the second image information into a color image. | 10-23-2014 |
Patent application number | Description | Published |
20090209756 | Emissive transition-metal complexes with both carbon-phosphorus ancillary and chromophoric chelates, synthetic method of preparing the same and phosphorescent organic light emitting diode thereof - The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligands being incorporated into a coordination sphere thereof with a transition metal, and one carbon-phosphorus (ĈP) chelate being incorporated into the coordination sphere; or ii) one carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligand forming a coordination sphere thereof with a transition metal, and two identical carbon-phosphorus (ĈP) chelates being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the chromophoric ligands possess a relatively lower energy gap in comparison with that of the non-chromophoric chelate, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that bright phosphorescence can be observed. The architecture and energy gap of the present molecular designs are suitable for generation of high efficiency blue, green and even red emissions. | 08-20-2009 |
20130005975 | EMISSIVE TRANSITION-METAL COMPLEXES WITH BOTH CARBON-PHOSPHORUS ANCILLARY AND CHROMOPHORIC CHELATES, SYNTHETIC METHOD OF PREPARING THE SAME AND PHOSPHORESCENT ORGANIC LIGHT EMITTING DIODE THEREOF - The present invention provides a phosphorescent tris-chelated transition metal complex having one carbon-nitrogen (ĈN) or nitrogen-nitrogen (N̂N) chromophoric ligand forming a coordination sphere thereof with a transition metal, and two identical carbon-phosphorus (ĈP) chelates being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the chromophoric ligands possess a relatively lower energy gap in comparison with that of the non-chromophoric chelate, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that bright phosphorescence can be observed. The architecture and energy gap of the present molecular designs are suitable for generation of high efficiency blue, green and even red emissions. | 01-03-2013 |
Patent application number | Description | Published |
20100027188 | Replaceable Electrostatic Chuck Sidewall Shield - A replaceable electrostatic chuck sidewall shield is provided. The replaceable electrostatic chuck sidewall shield fills or partially fills an indentation located between a base member and a top member of an electrostatic chuck, such that the replaceable electrostatic chuck sidewall shield may protect an epoxy in the indentation or may replace the epoxy within the indentation. The replaceable electrostatic chuck sidewall shield may be fully contained with the indentation. The replaceable electrostatic chuck sidewall shield may also cover an epoxy in the indentation such that the replaceable electrostatic chuck sidewall shield protrudes beyond the indentation. In an alternate embodiment, the replaceable electrostatic chuck sidewall shield substantially covers the area in which a conductive pole is embedded in a bipolar electrostatic chuck. | 02-04-2010 |
20100089744 | Method for Improving Adhesion of Films to Process Kits - A method includes providing a process chamber including a target, wherein the target has a first coefficient of thermal expansion (CTE); selecting a process kit including a surface layer having a second CTE close to the first CTE; and installing the process kit in the process chamber with the surface layer exposed to the process chamber. A ratio of a difference between the first CTE and the second CTE is less than about 35 percent. | 04-15-2010 |
20110035043 | METHOD AND APPARATUS FOR WIRELESS TRANSMISSION OF DIAGNOSTIC INFORMATION - The present disclosure provides a system for fabricating a semiconductor device. The system includes a semiconductor fabrication tool. The semiconductor fabrication tool has an integrated inter interface that measures a first process parameter of the fabrication tool. The system also includes a wireless sensor. The wireless sensor is detachably coupled to the fabrication tool. The wireless sensor measures a second process parameter of the fabrication tool. The second process parameter is different from the first process parameter. | 02-10-2011 |
20110035186 | PORTABLE WIRELESS SENSOR - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 02-10-2011 |
20110207332 | THIN FILM COATED PROCESS KITS FOR SEMICONDUCTOR MANUFACTURING TOOLS - A plasma processing apparatus used in semiconductor device manufacturing includes a process kit formed of insulating materials such as quartz and coated with a Y | 08-25-2011 |
20120289069 | Apparatus for Blocking I/O Interfaces of Computing Devices - An input/output (I/O) interface blocking device includes a fitting member. The fitting member includes a protruding portion, which includes a first sidewall and a second sidewall opposite to each other. The first sidewall is slanted in a direction allowing the first fitting member to be inserted into a space in an I/O interface receptacle. The second sidewall is configured to block the fitting member from being pulled out of the space in the I/O interface receptacle. | 11-15-2012 |
20130026381 | DYNAMIC, REAL TIME ULTRAVIOLET RADIATION INTENSITY MONITOR - An apparatus and method for detecting an intensity of radiation in a process chamber, such as an ultraviolet curing process chamber, is disclosed. An exemplary apparatus includes a process chamber having a radiation source therein, wherein the radiation source is configured to emit radiation within the process chamber; a radiation sensor attached to the process chamber; and an optical fiber coupled with the radiation source and the radiation sensor, wherein the optical fiber is configured to transmit a portion of the emitted radiation to the radiation sensor, and the radiation sensor is configured to detect an intensity of the portion of the emitted radiation via the optical fiber. | 01-31-2013 |
20140008213 | MAGNET MODULE HAVING EPICYCLIC GEARING SYSTEM AND METHOD OF USE - This disclosure relates to a magnet assembly including an epicyclic gearing system. The epicyclic gearing system including a central gear configured to be rotated, at least one peripheral gear connected to the central gear and configured to rotate and translate relative to the central gear, and an annulus surrounding the at least one peripheral gear and connected with the at least one peripheral gear. The magnet assembly further includes a magnet module connected with the epicyclic gearing system, the magnet module including a support connected with the at least one peripheral gear, the axis of rotation of the support being coaxial with the axis of rotation of the at least one peripheral gear connected with the support. | 01-09-2014 |
20140200702 | Digital Wireless Data Collection - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The first and second sensors may communicate the parameters using different and incompatible protocols. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 07-17-2014 |
20140273293 | Portable Wireless Sensor - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 09-18-2014 |
Patent application number | Description | Published |
20100315459 | METHOD FOR PRINTING ON A CURVED SURFACE - A method for printing on a curved surface includes determining if a surface of a workpiece is curved, cutting an image to be printed into at least two printing areas if the surface is curved, and printing the printing area of the image on each surface of the workpiece. If the surfaces of the workpiece are not curved, the printing system directly prints the image on the workpiece. The printing system includes a rotating mechanism and a printer including an inkjet head having a plurality of nozzles. The workpiece is positioned on the rotating mechanism. The rotating mechanism rotates each surface of the workpiece to face the inkjet head and the inkjet head prints each printing area on it. | 12-16-2010 |
20110012952 | METHOD FOR PRINTING ON A WORKPIECE - A three-dimensional continuous printing method on a workpiece positioned on a rotation mechanism is described. The rotation mechanism rotates the print area of the surface of the workpiece to face the inkjet head of the printer. The inkjet head of the printer prints on the print area of the surface of the workpiece. A selection of additional print areas is offered. If the selection is requested, the rotation mechanism rotates the workpiece such that the desired print area faces the inkjet head of the printer, and selection of the other print area of the workpiece for print is confirmed. If not, the printing process is completed. | 01-20-2011 |
20120169806 | KEY LABELING METHOD - A method for printing a label on a keypad, including the steps of providing a substrate plate, spraying ink on the substrate plate to form a label layer, solidifying the label layer, spraying ink around the label layer to form a primer layer, and solidifying the primer layer. | 07-05-2012 |
20120171399 | HOUSING AND METHOD FOR MANUFACTURING THE SAME - A housing includes a base layer, a primer layer formed on the base layer, an ink jet coating layer formed on the primer layer, and a protection layer formed on the ink jet coating layer. A method for manufacturing the housing is also provided. | 07-05-2012 |
Patent application number | Description | Published |
20080298715 | IMAGE ANALYSIS METHOD - The present invention relates to an image analysis method for analyzing an image. By inputting starting point coordinates and ending point coordinates of individual image blocks contained in the image, an image block arrangement table is created. The image is analyzed according to the image block arrangement table. | 12-04-2008 |
20090262204 | NOTEBOOK COMPUTER - The present invention relates to a notebook computer for capturing an image of a card. The notebook computer includes a base and an upper cover. The base includes a keyboard and a fixing recess for fixing the card. The upper cover is pivotally coupled to the base and includes an image sensing device and a screen for displaying a frame. If the image sensing device is disenabled to capture the image of the card, the frame on the screen has a first luminance value. Whereas, if the image sensing device is enabled to capture the image of the card, the frame on the screen has a second luminance value greater than the first luminance value. | 10-22-2009 |
20090262209 | NOTEBOOK COMPUTER AND METHOD OF CAPTURING DOCUMENT IMAGE USING IMAGE PICKUP DEVICE OF SUCH NOTEBOOK COMPUTER - The present invention relates to a notebook computer. The notebook computer includes a base and an upper cover. The base has a keyboard. The upper cover includes a screen, an image pickup device and a close-up lens. The upper cover is rotatable with respect to the base such that the image pickup device is able to capture an image of a document on a working plane. After the document image is obtained by the image pickup device, a built-in image processing program performs correction on the document image so as to obtain a corrected document image. | 10-22-2009 |
20100245597 | AUTOMATIC IMAGE CAPTURING SYSTEM - An automatic image capturing system includes a computer, an image capturing device, a monitor and an automatic image capturing program. The automatic image capturing program is installed in the computer. The image capturing device is used for capturing an image of a target object. The monitor is used for displaying shooting area. If a pre-shot image of the target object is moved to be within the shooting area, the automatic image capturing program will automatically capture the image of the target object. | 09-30-2010 |
20110149088 | IMAGE PICKUP SYSTEM - An image pickup system includes a base, a frame, an image pickup device, a receiving structure, a marking element and a switching element. The frame is connected to the base. The image pickup device is disposed on the frame. The receiving structure is disposed in the base. The frame is rotatable with respect to the base, so that the image pickup device is moved to an optimal shooting position. The marking element indicates that the image pickup device is at the optimal shooting position. When the switching element is triggered, the target object placed in the receiving structure will be shot by the image pickup device. | 06-23-2011 |
20120007993 | IMAGE PICKUP SYSTEM - An image pickup system includes a display screen, an image pickup device and a positioning program. The image pickup device is used for shooting a document. The display screen is used for showing a positioning mark. When the document is moved and a pre-shot document image is aligned with the positioning mark, the image pickup device is activated by the positioning program to shoot the document, thereby obtaining a document image. | 01-12-2012 |
20120113006 | MOUSE WITH SHOOTING FUNCTION AND IMAGE PICKUP SYSTEM - A mouse with a shooting function and an image pickup system are provided. The image pickup system includes a mouse and a computer system. A shooting program is installed in the computer system. The mouse includes an image pickup device and a supporting member. The supporting member is used for fixing a business card. The shooting program is executed to judge whether the business card is separated from the image pickup device by a shooting distance, which is equal to a focal length of the image pickup device. If the business card is separated from the image pickup device by the shooting distance, the image pickup device is enabled by the shooting program to shoot the business card, thereby acquiring a business card image. | 05-10-2012 |
Patent application number | Description | Published |
20110108894 | METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material. | 05-12-2011 |
20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 06-23-2011 |
20120126296 | INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region | 05-24-2012 |
20130023094 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid. | 01-24-2013 |
20130328126 | EPITAXIAL FORMATION OF SOURCE AND DRAIN REGIONS - Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues. | 12-12-2013 |
20140246710 | CYCLIC DEPOSITION ETCH CHEMICAL VAPOR DEPOSITION EPITAXY TO REDUCE EPI ABNORMALITY - A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described. | 09-04-2014 |
20140264348 | Asymmetric Cyclic Desposition Etch Epitaxy - The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed. | 09-18-2014 |
20140299945 | INTEGRATED CIRCUITS HAVING SOURCE/DRAIN STRUCTURE - An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region. | 10-09-2014 |
Patent application number | Description | Published |
20110210404 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 09-01-2011 |
20120299121 | Source/Drain Formation and Structure - A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region. | 11-29-2012 |
20130001705 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 01-03-2013 |
20130062670 | Device with Engineered Epitaxial Region and Methods of Making Same - An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps. | 03-14-2013 |
Patent application number | Description | Published |
20120329280 | METHOD FOR FORMING PHOTORESIST PATTERNS - A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index. | 12-27-2012 |
20130017474 | METHOD OF FORMING ASSIST FEATURE PATTERNSAANM Chiang; Yi-ChihAACI Tainan CityAACO TWAAGP Chiang; Yi-Chih Tainan City TWAANM Pai; Yuan-ChiAACI Tainan CityAACO TWAAGP Pai; Yuan-Chi Tainan City TWAANM Lee; Sho-ShenAACI New Taipei CityAACO TWAAGP Lee; Sho-Shen New Taipei City TWAANM Chen; Yi-TingAACI Kaohsiung CityAACO TWAAGP Chen; Yi-Ting Kaohsiung City TWAANM Yu; Tuan-YenAACI Tainan CityAACO TWAAGP Yu; Tuan-Yen Tainan City TW - A method of forming assist feature patterns includes providing an original layout pattern having at least a first region defined therein, the first region having a first light transmission rate larger than 0%; performing a search step to the original layout pattern to define at least a second region having a second light transmission rate equal to 0% in the original layout pattern; forming a plurality of assist features in the second region to increase the second light transmission rate to larger than 0%; and outputting the original layout pattern and the assist features to a reticle blank. | 01-17-2013 |
20130200535 | OVERLAY MARK FOR MULTIPLE PRE-LAYERS AND CURRENTLY LAYER - An overlay mark is described, including N (N≧2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately. | 08-08-2013 |
20130210237 | PHOTORESIST REMOVAL METHOD AND PATTERNING PROCESS UTILIZING THE SAME - A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed. | 08-15-2013 |
20140120476 | Method of forming a photoresist pattern - A method of forming a photoresist pattern, in which, a substrate is coated with a photoresist layer, an exposure process is performed on the photoresist layer to expose the photoresist layer, the photoresist layer is rinsed with a surfactant after the exposure process is performed, and the photoresist layer is post-exposure baked after the photoresist layer is rinsed with the surfactant. | 05-01-2014 |
20150064861 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate. | 03-05-2015 |
Patent application number | Description | Published |
20120326305 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved. | 12-27-2012 |
20130026657 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area. | 01-31-2013 |
20130228921 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure. | 09-05-2013 |
20130307152 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 11-21-2013 |
20140308780 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 10-16-2014 |