Patent application number | Description | Published |
20100086197 | WAFER EDGE INSPECTION AND METROLOGY - Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit. | 04-08-2010 |
20110054659 | WAFER FABRICATION MONITORING SYSTEMS AND METHODS, INCLUDING EDGE BEAD REMOVAL PROCESSING - Systems and method for monitoring semiconductor wafer fabrication processing, for example based upon EBR line inspection, including capturing at least one image of a wafer at an intermediate stage of fabrication. The captured image(s) are compressed to generate a composite representation of at least an edge zone of the wafer. An edge bead removal area is identified in the representation, and at least one feature attribute is extracted from the identified area. The extracted feature attribute is automatically assessed, and information relating to a status of the fabrication processing in generated based upon the assessment. For example, recommended modifications to the fabrication processing, either upstream or downstream of the current stage of fabrication (or both) can be generated and implemented. | 03-03-2011 |
20110085725 | WAFER EDGE INSPECTION AND METROLOGY - Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit. | 04-14-2011 |
20110263049 | WAFER EDGE INSPECTION - Wafer edge inspection approaches are disclosed wherein an imaging device captures at least one image of an edge of a wafer. The at least one image can be analyzed in order to identify an edge bead removal line. An illumination system having a diffuser can further be used in capturing images. | 10-27-2011 |
20130022260 | WAFER EDGE INSPECTION AND METROLOGY - Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit. | 01-24-2013 |
20140063799 | WAFER EDGE INSPECTION - Wafer edge inspection approaches are disclosed wherein an imaging device captures at least one image of an edge of a wafer. The at least one image can be analyzed in order to identify an edge bead removal line. An illumination system having a diffuser can further be used in capturing images. | 03-06-2014 |
Patent application number | Description | Published |
20080296253 | Method and apparatus to change solder pad size using a differential pad plating - A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps. | 12-04-2008 |
20090250506 | Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards - A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface. | 10-08-2009 |
20100175248 | System and method of using a compliant lead interposer - The present invention relates to a compliant leaded interposer for resiliently attaching and electrically connecting a ball grid array package to a circuit board. The interposer may include a substrate, a plurality of pads, and a plurality of pins. The plurality of pads may be positioned substantially on the top surface of the substrate and arranged in a predetermined pattern substantially corresponding to the solder ball pattern on the ball grid array package. The plurality of pins may be positioned substantially perpendicular to the substrate and may extend through the substrate and the plurality of pads. The interposer may be configured to attach the ball grid array package to the circuit board such that each of the solder balls on the ball grid array package contacts at least a portion the plurality of pins and at least a portion of the plurality of pads and such that the each of the plurality of pins also connects to a contact on the circuit board. | 07-15-2010 |
20110101075 | Apparatus and methods of attaching hybrid vlsi chips to printed wiring boards - A method for preparing an integrated circuit for connection to a surface, the integrated circuit including lead contacts and leadless contacts, is provided. The method includes providing the integrated circuit, applying a first solder paste to the leadless contacts, forming solder balls on the applied solder paste, heating the solder balls, thereby removing at least a portion of the first solder paste and bringing the solder balls into electrical contact with the leadless contacts, the base of the solder balls being generally aligned in a plane, and bending the lead contacts into gull wings, with the base of the gull wings being substantially coplanar with the plane. The base of the gull wings and the base of the at least one of the solder balls collectively generally define a contact plane for potential future contact with the surface. | 05-05-2011 |
20110157855 | INTEGRATED CIRCUITS HAVING LEAD CONTACTS AND LEADLESS CONTACT PADS CONNECTED TO A SURFACE OF A PRINTED WIRING BOARD, AND METHODS FOR CONNECTING THE SAME - A method is provided for connecting an integrated circuit to a surface of a printed wiring board. The integrated circuit includes lead contacts and leadless contact pads. A first solder paste is applied to the leadless contact pads of the integrated circuit, and preformed conductive pieces are placed on the first solder paste. The preformed conductive pieces are slugs that have, for example, a cylindrical shape or a rectangular cross-section. The preformed conductive pieces are heated and brought into electrical contact with the leadless contact pads. The lead contacts are formed into gull wings. The bases of the preformed conductive pieces are generally aligned in a plane, and the bases of the gull wings are substantially coplanar with the plane such that they collectively generally define a contact plane. A second solder paste is applied on the surface, and the bases of the gull wings and the preformed conductive pieces are soldered to the second solder paste on the surface so that the integrated circuit is in electrical contact with the surface through both the leadless contact pads and the lead contacts. The preformed conductive pieces comprise a conductive material (e.g., a copper alloy) that has a higher melting point than the first solder paste and the second solder paste such that the preformed conductive pieces do not melt during heating or soldering that is described above. | 06-30-2011 |