Patent application number | Description | Published |
20140097478 | REDUCED CHARGE TRANSISTOR - Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor. | 04-10-2014 |
20140231883 | Vertical JFET with Integrated Body Diode - A vertical junction field effect transistor (JFET) includes a drain, a source, a gate, a drift region, and a body diode. The source, gate, drift region, and body diode are all disposed in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source. | 08-21-2014 |
20150069411 | SEMICONDUCTOR DEVICE, JUNCTION FIELD EFFECT TRANSISTOR AND VERTICAL FIELD EFFECT TRANSISTOR - A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate. | 03-12-2015 |
20150076568 | Junction Field Effect Transistor with Vertical PN Junction - An embodiment relates to a JFET with a channel region and a gate region forming a pn junction. Between a source region and a drain region in a semiconductor portion, the pn junction extends along a vertical direction perpendicular to a first surface of the semiconductor portion. The source, channel and drain regions have a first conductivity type and are arranged along the vertical direction. The gate region and a shielding region between the gate and drain regions have a second, complementary conductivity type. An auxiliary region separates the gate and shielding regions in the semiconductor portion. | 03-19-2015 |