Patent application number | Description | Published |
20080224348 | PRESS-MOLDING APPARATUS AND WORK-CONVEYING METHOD IN THE APPARATUS - There are provided a press-molding apparatus and a work-conveying method, which are capable of restraining oxygen from entering the molding apparatus when a work, such as a mold or a material, is carried into the molding apparatus. | 09-18-2008 |
20080282737 | PRESS-MOLDING APPARATUS - The invention provides a press-molding apparatus having, disposed on a conveying passageway: a heating chamber for heating a mold containing a raw material placed therein; a molding chamber for press-molding the raw material in a non-oxidizing gas atmosphere; and a cooling chamber for cooling the mold after the molding, the mold being conveyed on the conveying passageway in order, each of the heating chamber, the molding chamber, and the cooling chamber being blocked from the atmosphere upon the press-molding, the press-molding apparatus having: a means for blocking the molding chamber and the cooling chamber; and an inflow port for introducing the non-oxidizing gas into the press-molding apparatus, the inflow port being formed for at least one of the heating chamber and the molding chamber. | 11-20-2008 |
20090026654 | MOLDING APPARATUS AND METHOD FOR CONVEYING CONVEYANCE OBJECT - The invention provides a molding apparatus having: an outside-air-blocking conveying passageway allowing a conveyance object passing therethrough; and a chamber having a non-oxidizing gas atmosphere, the outside-air-blocking conveying passageway having a blocking member having restoring force, the blocking member touching the conveyance object passing through the outside-air-blocking conveying passageway, at least one of the inlet side and outlet side of the outside-air-blocking conveying passageway being blocked with the blocking member upon the conveyance object passing through the outside-air-blocking conveying passageway, the outside-air-blocking conveying passageway having an overall length longer than that of the conveyance object. | 01-29-2009 |
Patent application number | Description | Published |
20080312761 | AUDIO PLAYING APPARATUS AND AUDIO PLAYING METHOD - An audio playing apparatus that plays a multiplexed audio stream resulting from the multiplexing of multiple kinds of audio is disclosed. The apparatus can be switched at least between a mixing output mode for mixing decoded data or uncompressed data of the audio streams of multiple kinds of audio and outputting the result to one audio output terminal and a separate output mode for outputting the audio streams of multiple kinds of audio to separate audio output terminals independently. | 12-18-2008 |
20090022324 | INFORMATION PROCESSING APPARATUS, CONTENT PROVIDING SYSTEM, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM - Disclosed herein is an information processing apparatus that serves as a server that performs data transmission in response to receipt of media information from a user device. The information processing apparatus includes: an encrypted transmission data storage database that stores a transmission data identifier and encrypted transmission data such that the transmission data identifier and the encrypted transmission data are associated with each other; and a control section configured to acquire, from a key management server, an encrypted unit key obtained by encrypting a unit key that is used to encrypt the transmission data, and transmit the acquired encrypted unit key and the encrypted transmission data to the user device. | 01-22-2009 |
20090245058 | INFORMATION PROCESSING APPARATUS AND METHOD, PROGRAM, RECORDING MEDIUM, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus includes a measuring unit, a transmitter, and a receiver. The measuring unit first measures the performance of the information processing apparatus. The transmitter then transmits measurement results in the form of information indicating the performance measured by the measuring unit, together with a content request requesting desired content, to another information processing apparatus. The receiver subsequently receives content from the other information processing apparatus that has been supplied according to the content request and selected on the basis of the measurement results. In so doing, the information processing load is suitably adjusted according to the performance of the information processing apparatus. | 10-01-2009 |
20100121894 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, INFORMATION RECORDING MEDIUM, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a communicating section that executes communication with a server, a local storage section that stores subsequent data acquired from the server, and a data processing section that executes an acquisition process of the subsequent data, and a data playback process using data stored on a disc and the subsequent data stored on the local storage section. The data processing section builds a virtual file system for reading data stored on the disc and the local storage section, at the time of the data playback process, and performs the acquisition process of the subsequent data by transmitting a package ID to the server at the time of the acquisition process of the subsequent data, the package ID being information specifying a package corresponding to a file set necessary for building or updating the virtual file system. | 05-13-2010 |
Patent application number | Description | Published |
20090034353 | Semiconductor memory device - A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat. | 02-05-2009 |
20090279372 | SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER - In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number. | 11-12-2009 |
20100165693 | SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats. | 07-01-2010 |
20100195431 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 08-05-2010 |
20110292717 | Semiconductor device - A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines. | 12-01-2011 |
20120120706 | SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 05-17-2012 |
20120309156 | METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 12-06-2012 |
20130148412 | SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats. | 06-13-2013 |
20130301330 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. | 11-14-2013 |
20130308403 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT - Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. | 11-21-2013 |