Patent application number | Description | Published |
20140098683 | HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT - Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system. | 04-10-2014 |
20140115218 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
20140115298 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
20140177473 | HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS - A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers. | 06-26-2014 |
20140177648 | TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication. | 06-26-2014 |
20140204735 | AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT BY CAPTURING INTERNAL DEPENDENCIES OF IP CORES USING HIGH LEVEL SPECIFICATION - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. | 07-24-2014 |
20140204764 | QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS AND USING WEIGHTED ARBITRATION AT NOC NODES - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations. | 07-24-2014 |
20140211622 | CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC CONGESTION - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem. | 07-31-2014 |
20140254388 | RECONFIGURABLE NOC FOR CUSTOMIZING TRAFFIC AND OPTIMIZING PERFORMANCE AFTER NOC SYNTHESIS - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping. | 09-11-2014 |
20140301241 | MULTIPLE HETEROGENEOUS NOC LAYERS - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the topology of different NoC layers and maps system traffic flows to various routes in various NoC layers that satisfies the latency requirements of the flows. The number of layers and their topology is dynamically allocated and optimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers and updating the topology of the NoC layers as they are mapped. In addition to allocating additional NoC layers and topologies to satisfy the latency requirements of the flows, the NoC layers and topologies may also be allocated to satisfy the bandwidth requirements of the flows or to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various flows. | 10-09-2014 |
20140328172 | CONGESTION CONTROL AND QOS IN NOC BY REGULATING THE INJECTION TRAFFIC - Systems and methods described herein are directed to solutions for NoC interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair allocation of resource bandwidths among various contenders in a mesh or torus interconnect. The example implementations are fully distributed and involve using explicit congestion notification messages or local congestion identification for congestion detection. Based on the congestion level detected, the injection rates of traffic at various agents are regulated that avoids congestion and also provides end-to-end QoS. Alternative example implementations may also utilize end-to-end credit based flow control between communicating agents for resource and bandwidth allocation of the destination between the contending sources. The resource allocation is performed so that both the weighted and strict bandwidth allocation QoS policies are satisfied. | 11-06-2014 |
20140328208 | HETEROGENEOUS SOC IP CORE PLACEMENT IN AN INTERCONNECT TO OPTIMIZE LATENCY AND INTERCONNECT PERFORMANCE - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded. | 11-06-2014 |
20140331027 | ASYMMETRIC MESH NOC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links | 11-06-2014 |
20150016257 | IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FOR EVALUATING POTENTIAL PROTOCOL LEVEL DEADLOCKS - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels. | 01-15-2015 |
20150032437 | SYSTEM LEVEL SIMULATION IN NETWORK ON CHIP ARCHITECTURE - Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect. | 01-29-2015 |
20150036536 | AUTOMATIC NoC TOPOLOGY GENERATION - Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts. | 02-05-2015 |
20150043575 | SUPPORTING MULTICAST IN NOC INTERCONNECT - Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein. | 02-12-2015 |