Patent application number | Description | Published |
20090045839 | ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE - A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides. | 02-19-2009 |
20090153324 | DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT - An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. | 06-18-2009 |
20090157334 | MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT - An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. | 06-18-2009 |
20090183134 | DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. | 07-16-2009 |
20090183135 | Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes - A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 07-16-2009 |
20090268541 | DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded. | 10-29-2009 |
20100017773 | Method for Minimizing Impact of Design Changes For Integrated Circuit Designs - A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change. | 01-21-2010 |
20120083913 | SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE - A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location. | 04-05-2012 |
20120167022 | METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 06-28-2012 |