Nishioka, Kanagawa
Daisuke Nishioka, Kanagawa JP
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20120020875 | CATALYST FOR REDUCING NITROGEN OXIDES AND METHOD FOR PRODUCING THE SAME - The object is to provide an exhaust gas reduction catalyst that exhibit high nitrogen oxide reduction performance, and to provide a simple and efficient method for producing the catalyst, in which the amount of the waste liquid is reduced, further, an object of the invention is to provide a zeolite-containing catalyst for reducing nitrogen oxides, which does not use an expensive noble metal or the like and which has high nitrogen oxide reduction performance. The present invention relates to a catalyst for reducing nitrogen oxides, which comprises: zeolite at least containing an aluminium atom and a phosphorus atom in the framework thereof; and a metal supported on the zeolite, wherein a coefficient of variation of intensity of the metal is at least 20%, when performing an elemental mapping of the metal in the catalyst with an electron probe microanalyzer, and, a catalyst for reducing nitrogen oxides, which comprises the zeolite containing at least a silicon atom, a phosphorus atom and an aluminium atom, and having an adsorption retention rate of at least 80% in a water vapor cyclic adsorption/desorption test at 90° C. | 01-26-2012 |
20120028789 | CATALYST FOR REDUCING NITROGEN OXIDES AND METHOD FOR PRODUCING THE SAME - The object is to provide an exhaust gas reduction catalyst that exhibit high nitrogen oxide reduction performance, and to provide a simple and efficient method for producing the catalyst, in which the amount of the waste liquid is reduced, further, an object of the invention is to provide a zeolite-containing catalyst for reducing nitrogen oxides, which does not use an expensive noble metal or the like and which has high nitrogen oxide reduction performance. The present invention relates to a catalyst for reducing nitrogen oxides, which comprises: zeolite at least containing an aluminium atom and a phosphorus atom in the framework thereof; and a metal supported on the zeolite, wherein a coefficient of variation of intensity of the metal is at least 20%, when performing an elemental mapping of the metal in the catalyst with an electron probe microanalyzer, and, a catalyst for reducing nitrogen oxides, which comprises the zeolite containing at least a silicon atom, a phosphorus atom and an aluminium atom, and having an adsorption retention rate of at least 80% in a water vapor cyclic adsorption/desorption test at 90° C. | 02-02-2012 |
20130005563 | CATALYST FOR REDUCING NITROGEN OXIDES AND METHOD FOR PRODUCING THE SAME - The object is to provide a nitrogen oxide reduction catalyst, which comprises zeolite containing at least a silicon atom, a phosphorus atom and an aluminium atom, and has an adsorption retention rate of at least 80%, when tested in a water vapor cyclic adsorption/desorption test at 90° C. It is also an object to provide a nitrogen oxide reduction device containing the foregoing catalyst on a honeycomb-structure formed article. | 01-03-2013 |
20130281284 | CATALYST FOR NITROGEN OXIDE REMOVAL - [Object] To provide a catalyst for nitrogen oxide removal having no degradation problem caused by adsorbed water when a temperature is raised sharply and exhibiting excellent nitrogen oxide removal performance and retentive characteristic thereof. | 10-24-2013 |
Daizo Nishioka, Kanagawa JP
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20090252460 | OPTICAL CONNECTOR AND METHOD OF ATTACHING OPTICAL FIBER CORD TO OPTICAL CONNECTOR - An optical connector has a simple structure and a method of attaching an optical fiber cord to the connector is easy. The connector | 10-08-2009 |
Daizou Nishioka, Kanagawa JP
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20100086258 | OPTICAL FIBER CONNECTOR AND OPTICAL CABLE - An optical fiber connector | 04-08-2010 |
Kaoru Nishioka, Kanagawa JP
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20130276677 | LOADING STRUCTURE - A loading structure includes a bottom plate on which an object is placed; a support stand that supports the bottom plate from below the bottom plate; a pair of first poles that stand on the support stand; a pair of second poles that stand on the support stand; a first beam located on a far side of the loading structure and extending in a left-right direction, the first beam being fixed to upper portions of the pair of second poles; a pair of second beams extending toward the far side, a distance between inner surfaces of the pair of second beams being larger than a distance between outer surfaces of the pair of second poles; and a supporting member that stands on the support stand on the far side, the supporting member supporting a far-side surface of the object placed on the bottom plate. | 10-24-2013 |
Kazuaki Nishioka, Kanagawa JP
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20140211061 | SOLID-STATE IMAGE CAPTURE DEVICE AND DRIVE METHOD THEREFOR - A solid-state image capture device includes; a solid-state imaging element having output portions configured to output signals read from pixels; samplers provided for the respective output portions and configured to sample the signals output from the output portions of the solid-state imaging element; and a controller configured to vary, at the samplers, sampling timings at which the samplers sample the signals or to vary, at the output portions, output characteristics with which the output portions output the signals read from the pixels. | 07-31-2014 |
Koichi Nishioka, Kanagawa JP
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20100103564 | TUNNEL JUNCTION TYPE MAGNETO-RESISTIVE HEAD - As recording density of sensors is increased, it is desired to lower the areal resistivity (RA) of TMR sensors. Decreasing RA to 1.0 Ωμm | 04-29-2010 |
20130164549 | Half Metal Trilayer TMR Reader with Negative Interlayer Coupling - In an embodiment of the invention, a trilayer magnetoresistive sensor comprises an underlayer on which a first free layer is deposited. A barrier layer is then deposited after which a second free layer is deposited. A capping layer is then deposited above second free layer. The first free layer is a layer which includes at least a layer of a nitride of an element including at least one of Fe, Co, or Ni, or a multiple laminate structure of a layer containing a nitride of an element including at least one of Fe, Co, Ni and another ferromagnetic layer containing at least one of Fe, Co, or Ni. The combination of the first and second free layers causes anti-parallel coupling. | 06-27-2013 |
Nobutaka Nishioka, Kanagawa JP
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20090058856 | IMAGE GENERATING APPARATUS, METHOD OF GENERATING IMAGE, PROGRAM, AND RECORDING MEDIUM - The object is to smoothly move the position of the viewing point of the virtual camera with existence of an object between the position of the viewing point of the virtual camera and the position of the subject avoided. A camera peripheral area that has a viewing point as its center and has the radius of R, a subject peripheral area that has a subject toward which a viewing axis of the virtual camera is aligned as its center and has the radius of r, and a camera-to-subject area formed by a circular truncated cone area therebetween are set as a camera collision in which an obstacle cannot exist. When an obstacle exists in the camera collision, the position of the viewing point is adjusted. The radius R and the radius r are adjusted each time the reference distance D is changed. | 03-05-2009 |
20090137321 | ONLINE GAME SYSTEM AND ONLINE GAME PROGRAM - In an online game server, an updater updates at least one of a game program and game data for server stored in a storage section in accordance with an update operation for data to be utilized when to execute a sub game other than a main game in an online game. Updated portion data are a shared library format that can be utilized in the client terminal. A transmitter transmits updated data including at least the updated portion data to the client terminal. In a client terminal, a rewriter rewrites at least one of a game program and game data for client stored in a memory. In the case where there is a specification operational input by a player, a controller controls progress of the online game using the game program or the game data for client without carrying out communication with the online game server. | 05-28-2009 |
Satoru Nishioka, Kanagawa JP
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20090019412 | DESIGN METHOD AND DESIGN APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT - According to the present invention, timing information, connection information and physical information are received, and at the weighting determination step, the degree to which a cell can move is weighted. Then, at the movement range determination step, the movement enabled range of the cell is determined, and whether or not a cell placement area is available is decided. When it is decided that a cell placement area is available, the processing advances either to the cell movement area extension step or to the cell placement area acquisition step. Thereafter, an automatic, optimal placement process is performed for the cell. | 01-15-2009 |
Shinichiro Nishioka, Kanagawa JP
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20120120960 | NODE DEVICE, INTEGRATED CIRCUIT AND CONTROL METHOD IN RING TRANSMISSION SYSTEM - A node device in a ring transmission system in which a plurality of node devices are connected as a ring via serial links has a PHY transitioning between a normal mode and a loopback mode with timing that maintains symbol lock between an idle frame transmitted to a later serial link in the normal mode according a transmission instruction, and an idle frame from an earlier node device looped back for output to a later serial link during the loopback mode, thus performing relay processing on non-locally addressed data packets during the loopback mode. | 05-17-2012 |
Soshiro Nishioka, Kanagawa JP
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20140320223 | SEMICONDUCTOR APPARATUS, OSCILLATION CIRCUIT, AND SIGNAL PROCESSING SYSTEM - A semiconductor apparatus includes: first and second external terminals that are connected to respective both ends of an piezoelectric vibrator, in which the piezoelectric vibrator is externally disposed; an inverting amplifier that is disposed between the first and second external terminals; a feedback resistance that feeds back an output of the inverting amplifier to an input of the inverting amplifier; a first capacitative element that is disposed between the first external terminal and a reference voltage terminal; a first resistive element that is disposed in series with the first capacitative element; a second capacitative element that is disposed between the second external terminal and the reference voltage terminal; and a second resistive element that is disposed in series with the second capacitative element. | 10-30-2014 |
Takahiro Nishioka, Kanagawa JP
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20100128383 | DISK DRIVE AND METHOD FOR CONTROLLING CLEARANCE IN THE DISK DRIVE - A disk drive. The disk drive includes a disk configured to store data, a slider configured to fly in proximity to the disk, and a magnetic-recording head on the slider configured to access the disk. The disk drive also includes a moving mechanism configured to support and to move the head-slider, an adjustment portion configured to adjust clearance between the magnetic-recording head and the disk, and a controller configured to control the adjustment portion to control the clearance. The controller is configured to perform clearance control in a first mode in an operation selected from the group consisting of reading user data and writing user data according to a change in fly height of the slider after a load operation, and subsequently is configured to perform clearance control in a second mode in an operation selected from the group consisting of reading user data and writing user data. | 05-27-2010 |
Yasutaka Nishioka, Kanagawa JP
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20120037968 | SOLID-STATE IMAGE SENSING DEVICE AND METHOD OF MANUFACTURING THE SAME - By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other. | 02-16-2012 |
Yuichiro Nishioka, Kanagawa JP
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20090277592 | Screen apparatus - A screen is made to be able to be interchanged in a state in which the screen is made to be detachable from a screen attaching frame portion, a first connector is arranged at one ends extracted from the screen of screen tension members penetrating the screen at a plurality of portions in a length direction, the one end is connected to a vicinity of a free end of a slide guide frame portion, other end of a jump member extracted to a screen attaching side is arranged with a second connector, the first connector and the second connector are made to be attachable and detachable to and from each other, and the slide guide frame portion is extracted from inside of the screen attaching frame portion. | 11-12-2009 |
20100096093 | SCREEN DEVICE - A weight moving in a height direction interlocking with development and reception of a slide guide frame is provided, and the weight brakes reception of the slide guide frame owing to an increase in potential energy and promotes development of the slide guide frame owing to a decrease in potential energy, whereby an operating force is decreased, a feeling of operating a slide bar is made light, and the slide bar is decreased in sliding speed at the time of closing to achieve an improvement in safety. | 04-22-2010 |
Yuya Nishioka, Kanagawa JP
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20120249204 | FLIP-FLOP CIRCUIT, SCAN TEST CIRCUIT, AND METHOD OF CONTROLLING SCAN TEST CIRCUIT - Provided is a flip-flop circuit which a small-sized test circuit with hold free and can perform test in an actual operating frequency. A Pos-type F/F includes a master latch (Low level latch) that selectively receives data or scan test data in synchronization with a rising edge of a clock signal, and a slave latch (High level latch) that receives the data from the master latch. In a scan shift operation, the master latch captures scan data signal input SIN in a Low period of a scan shift clock signal SCLK | 10-04-2012 |