Patent application number | Description | Published |
20080299782 | Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds - The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR | 12-04-2008 |
20090001443 | NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed. | 01-01-2009 |
20090008702 | DIELECTRIC CHARGE-TRAPPING MATERIALS HAVING DOPED METAL SITES - Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated. | 01-08-2009 |
20090045447 | COMPLEX OXIDE NANODOTS - Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate. | 02-19-2009 |
20090057744 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 03-05-2009 |
20090215262 | ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING SILICON-CONTAINING TANTALUM PRECURSOR COMPOUNDS - The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR | 08-27-2009 |
20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 11-19-2009 |
20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 12-31-2009 |
20100197131 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 08-05-2010 |
20100258857 | Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor - This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated. | 10-14-2010 |
20110049606 | CHARGE-TRAP BASED MEMORY - Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described. | 03-03-2011 |
20110062511 | DEVICE HAVING COMPLEX OXIDE NANODOTS - Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric. | 03-17-2011 |
20110133265 | MEMORY CELL - A memory cell has a tunnel dielectric over a first silicon-containing material, a second silicon-containing material over the tunnel dielectric, a first silicon oxide layer on an edge of the second silicon-containing material and extending across a first portion of an edge of the tunnel dielectric, and a second silicon oxide layer on a side of the first silicon-containing material and extending across a second portion of the edge of the tunnel dielectric. The first and second silicon oxide layers are two distinct layers and are in contact with the tunnel dielectric layer. | 06-09-2011 |
20110147827 | Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction. | 06-23-2011 |
20110180865 | CHARGE STORAGE NODES WITH CONDUCTIVE NANODOTS - Memory cells formed to include a charge storage node having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems. | 07-28-2011 |
20110248334 | MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS - Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described. | 10-13-2011 |
20120007037 | CROSS-POINT MEMORY UTILIZING Ru/Si DIODE - Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide. | 01-12-2012 |
20120032252 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 02-09-2012 |
20120104343 | Nonvolatile Memory Cells and Methods Of Forming Nonvolatile Memory Cell - A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed. | 05-03-2012 |
20120319172 | CHARGE-TRAP BASED MEMORY - Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described. | 12-20-2012 |
20130187121 | CROSS-POINT MEMORY UTILIZING RU/SI DIODE - Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide. | 07-25-2013 |
20140138753 | Transistors, Memory Cells and Semiconductor Constructions - Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate. | 05-22-2014 |
20140159136 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 06-12-2014 |
20140302648 | CHARGE STORAGE NODES WITH CONDUCTIVE NANODOTS - Methods of forming memory cells having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems. | 10-09-2014 |
20140346424 | Cross-Point Memory Utilizing RU/SI Diode - Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface of ruthenium or ruthenium silicide between the silicon material and the ruthenium material. | 11-27-2014 |