Patent application number | Description | Published |
20140040531 | SINGLE-READ BASED SOFT-DECISION DECODING OF NON-VOLATILE MEMORY - A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs. | 02-06-2014 |
20140114937 | METHOD TO SHORTEN HASH CHAINS IN LEMPEL-ZIV COMPRESSION OF DATA WITH REPETITIVE SYMBOLS - An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a sequence of hash values in a table from a stream of data values with repetitive values, (ii) find two consecutive ones of the hash values in the sequence that have a common value and (iii) create a shortened hash chain by generating a pointer in the table at an intermediate location that corresponds to a second of the two consecutive hash values. The pointer generally points forward in the table to an end location that corresponds to a last of the data values in a run of the data values. | 04-24-2014 |
20140164868 | FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE - An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure. | 06-12-2014 |
20140164880 | ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY - An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. | 06-12-2014 |
20140181617 | MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION - An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry. | 06-26-2014 |
20140266815 | LEMPEL-ZIV DATA COMPRESSION WITH SHORTENED HASH CHAINS BASED ON REPETITIVE PATTERNS - Methods and apparatus are provided for Lempel-Ziv data compression with shortened hash chains based on repetitive multi-byte runs. Data is compressed by processing a sequence of data to identify a repetitive pattern, such as a multi-byte run; and providing indicators associated with the sequence of data of a start position and an end position of the repetitive pattern. The indicators of the start and end positions of the repetitive pattern may comprise, for example, flags associated with the positions. The indicators of the start and end positions of the repetitive pattern are processed to determine a sequence length of the repetitive pattern. In addition, a match can be identified in the sequence of data having a length that is greater than or equal to an offset of s bytes to identify a run comprised of an s-byte sequence. | 09-18-2014 |
20140286102 | Method of Optimizing Solid State Drive Soft Retry Voltages - A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER. | 09-25-2014 |
20150113205 | Systems and Methods for Latency Based Data Recycling in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. | 04-23-2015 |