Patent application number | Description | Published |
20090304124 | REDUCED-COMPLEXITY MULTIPLE-INPUT, MULTIPLE-OUTPUT DETECTION - A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations. | 12-10-2009 |
20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |
20100057977 | REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log | 03-04-2010 |
20100107030 | LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS - In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices. | 04-29-2010 |
20100131819 | LDPC DECODER VARIABLE NODE UNITS HAVING FEWER ADDER STAGES - In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and w | 05-27-2010 |
20100202082 | Systems and Methods for Variable Fly Height Measurement - Various embodiments of the present invention provide systems and methods for determining fly height. For example, a system for fly height determination is disclosed that includes a head assembly disposed in relation to a storage medium, a write channel, and a read circuit. The read circuit is operable to receive information from both the head assembly and the write channel. A frequency determination circuit is included that is operable to receive a first signal from the read circuit corresponding to information received from the write channel and to provide a first fundamental frequency and a first higher order frequency based on the first signal, and the frequency determination circuit is operable to receive a second signal from the read circuit corresponding to information received from the head assembly channel and to provide a second fundamental frequency and a second higher order frequency based on the second signal. A compensation variable calculation module is included that is operable to divide the first fundamental frequency by the first higher order harmonic to yield a compensation variable. A fly height calculation module is included that is operable to divide the second fundamental frequency by the second higher order harmonic and the compensation variable to yield an indication of a distance between the head assembly and the storage medium. | 08-12-2010 |
20100275088 | LOW-LATENCY DECODER - In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated. | 10-28-2010 |
20120087035 | Systems and Methods for Variable Compensated Fly Height Measurement - Various embodiments of the present invention provide systems and methods for determining fly height. | 04-12-2012 |