Patent application number | Description | Published |
20100244564 | Distributing power to an integrated circuit - A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed. The power supply cell comprises: a layer comprising conductive material, the conductive material providing a conduction path for current flowing from the first voltage supply to a portion of the integrated circuit to be powered and further providing a protection path for surge current flowing between the first voltage supply and an electrostatic discharge protection device and between the electrostatic discharge protection device and the second voltage supply; the conductive material forming a first conduction path for providing a path for current flowing between the first voltage supply and the portion of the integrated circuit to be powered and for providing a portion of the protection path for surge current flowing between the first voltage supply and the electrostatic discharge protection device and a second conduction path for providing a further portion of the protection path for surge current flowing between the second voltage supply and the electrostatic discharge protection device; wherein the conductive material is arranged such that the first conduction path has a significantly lower resistance than the second conduction path. | 09-30-2010 |
20110095804 | Apparatus and method providing an interface between a first voltage domain and a second voltage domain - An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal. | 04-28-2011 |
20120044608 | Receiver circuit with high input voltage protection - An integrated circuit | 02-23-2012 |
20140002156 | DUTY CYCLE CORRECTION WITHIN AN INTEGRATED CIRCUIT | 01-02-2014 |
20140139277 | CALIBRATION OF DELAY CHAINS - A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator. | 05-22-2014 |
20140177359 | METHOD AND APPARATUS FOR ALIGNING A CLOCK SIGNAL AND A DATA STROBE SIGNAL IN A MEMORY SYSTEM - A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided. The method comprising the steps of: putting the memory into a write levelling mode; incrementing an alignment delay applied to the data strobe signal until a transition point occurs at which a response of the memory to issuance of the data strobe signal transitions to an inverse state; performing an oversampling of the response of the memory over a selected interval following said transition point; repeating the steps of incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of the oversampling is in the inverse state; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of the clock signal, the identified clock cycle responsible for the transition point; and applying the selected alignment delay to the data strobe signal and applying a clock cycle selection to a data path in the system to match the identified clock cycle. | 06-26-2014 |
20140177377 | DATA SIGNAL RECEIVER AND METHOD OF CALIBRATING A DATA SIGNAL RECEIVER - A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal. The method comprises the steps of: receiving, on each bit of the multi-bit data signal, a sample of a predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative start timing value indicative of a start of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a relative end timing value indicative of an end of the predetermined data pattern; determining, for each bit of the multi-bit data signal, a mid-point timing value halfway between the relative start timing value and the relative end timing value; applying a bit timing delay to each bit of the multi-bit data signal such that the mid-point timing values are aligned; and applying a strobe timing delay to the associated data strobe signal to align the associated data strobe signal with the aligned mid-point timing values. | 06-26-2014 |
20140181568 | INTERFACE FOR CONTROLLING THE PHASE ALIGNMENT OF CLOCK SIGNALS FOR A RECIPIENT DEVICE - Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment. The calibration control circuitry controls the controllable delay circuit to generate a delay to the clock signal in dependence upon the delay that generated the alignment detected during calibration. | 06-26-2014 |
20140293718 | MEMORY CONTROLLER AND METHOD OF CALIBRATING A MEMORY CONTROLLER - A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value. | 10-02-2014 |
20140307514 | MEMORY CONTROLLER USING A DATA STROBE SIGNAL AND METHOD OF CALIBRATING DATA STROBE SIGNAL IN A MEMORY CONTROLLER - A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process comprises a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive. | 10-16-2014 |