Patent application number | Description | Published |
20140007133 | SYSTEM AND METHOD TO PROVIDE SINGLE THREAD ACCESS TO A SPECIFIC MEMORY REGION | 01-02-2014 |
20140136823 | Enabling A User And/Or Software To Dynamically Control Performance Tuning Of A Processor - In an embodiment, a processor includes a power control unit (PCU) to control power delivery to components of the processor and further including a storage having an overclock lock indicator which when set is to prevent a user from updating configuration settings associated with overclocking performance of the processor within an operating system (OS) environment. Other embodiments are described and claimed. | 05-15-2014 |
20140250291 | CONTINUATION OF TRUST FOR PLATFORM BOOT FIRMWARE - This disclosure is directed to continuation of trust for platform boot firmware. A device may comprise a processing module and a memory module including read-only memory (ROM) on which is stored platform boot firmware. On activation, the processing module may load the platform boot firmware. The platform boot firmware may cause the processing module to first load a trusted pre-verifier file to load and verify the signature of a hash table loaded from the platform boot firmware. The processing module may then load firmware program files from the platform boot firmware, calculate a hash for each file, and verify whether each program hash is in the hash table. Firmware program files with hashes in the hash table may be allowed to execute. If any firmware program file hash is not in the hash table, the processing module may perform platform specific security actions to prevent the device from being compromised. | 09-04-2014 |
20150095633 | TRUSTED BOOT AND RUNTIME OPERATION - An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor including secure non-volatile storage that couples to a root index, having a fixed address, and comprises first and second variables referenced by the root index; and semiconductor integrated code (SIC) including embedded processor logic to initialize a processor and embedded memory logic to initialize a memory coupled to the processor; wherein (a) the SIC is to be executed responsive to resetting the processor and prior to providing control to boot code, and (b) the SIC is to perform pre-boot operations in response to accessing at least one of the first and second variables. Other embodiments are described herein. | 04-02-2015 |
20150268970 | SELECTIVELY ENABLING PLATFORM-SPECIFIC FEATURES - Technologies for selectively enabling platform-specific features includes a computing device that initializes virtual device driver logic to interface with a virtual device of an Advanced Configuration and Power Interface (ACPI) subsystem. The ACPI subsystem includes an operating system (OS)-specific function specification associated with the virtual device. The OS-specific function specification includes OS-specific functions to be performed by the ACPI subsystem based on an identified OS. The virtual device driver logic transmits a call to the OS-specific function specification in the ACPI subsystem. The call includes an identifier of an OS of the computing device that uniquely identifies the OS from other operating systems. The ACPI subsystem analyzes the OS-specific function specification to determine OS-specific functions associated with the OS based on the identifier. The ACPI subsystem performs the determined OS-specific functions. | 09-24-2015 |
20150277778 | VIRTUAL GENERAL-PURPOSE I/O CONTROLLER - Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed. | 10-01-2015 |
20150378957 | EMPLOYING MULTIPLE I2C DEVICES BEHIND A MICROCONTROLLER IN A DETACHABLE PLATFORM - Methods and apparatus relating to employing multiple I2C (Interface to Communicate) devices behind a microcontroller in a detachable platform are described. In an embodiment, first logic receives a first message via a serial single ended (such as an Interface to Communicate (I2C)) bus. The first logic generates a second message to be transmitted to second logic in response to a determination that the first message is not directed to an address space assigned to the first logic. The second message includes information from the first message. Other embodiments are also disclosed. | 12-31-2015 |
20150379306 | Management of Authenticated Variables - An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor coupled to secure non-volatile storage; and at least one storage medium having firmware instructions stored thereon for causing, during runtime and after an operating system for the apparatus has booted, the cryptoprocessor to (a) store a key within the secure non-volatile storage, (b) sign an object with the key, while the key is within the cryptoprocessor, to produce a signature, and (c) verify the signature. Other embodiments are described herein. | 12-31-2015 |