Patent application number | Description | Published |
20080258198 | STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS - The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:
| 10-23-2008 |
20120097234 | Using Diffusion Barrier Layer for CuZnSn(S,Se) Thin Film Solar Cell - Techniques for fabricating thin film solar cells, such as CuZnSn(S,Se) (CZTSSe) solar cells are provided. In one aspect, a method of fabricating a solar cell is provided that includes the following steps. A substrate is provided. The substrate is coated with a molybdenum (Mo) layer. A stress-relief layer is deposited on the Mo layer. The stress-relief layer is coated with a diffusion barrier. Absorber layer constituent components are deposited on the diffusion barrier, wherein the constituent components comprise one or more of sulfur (S) and selenium (Se). The constituent components are annealed to form an absorber layer, wherein the stress-relief layer relieves thermal stress imposed on the absorber layer, and wherein the diffusion barrier blocks diffusion of the one or more of S and Se into the Mo layer. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20120100663 | Fabrication of CuZnSn(S,Se) Thin Film Solar Cell with Valve Controlled S and Se - Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20120270385 | SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE - A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate. | 10-25-2012 |
20140001440 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES | 01-02-2014 |
20140034118 | THIN FILM SOLAR CELLS - Embodiments relate to a solar cell apparatus including a molybdenum (Mo) contact layer and an annealed absorber layer including zinc and sulfur directly adjacent to the Mo contact layer. The apparatus has no molybdenum disulfide (MoS | 02-06-2014 |
20140038344 | THIN FILM SOLAR CELLS - Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS | 02-06-2014 |
20140113416 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES - A method for fabricating a carbon-based semiconductor device. A substrate is provided and source/drain contacts are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts. | 04-24-2014 |
20150377702 | Spectrometer Insert for Measuring Temperature-Dependent Optical Properties - In one aspect, a spectrometer insert is provided. The spectrometer insert includes: an enclosed housing; a first transparent window on a first side of the enclosed housing; a second transparent window on a second side of the enclosed housing, wherein the first side and the second side are opposing sides of the enclosed housing; and a sample mounting and heating assembly positioned within an interior cavity of the enclosed housing in between, and in line of sight of, the first transparent window and the second transparent window. A method for using the spectrometer insert to locally heat a sample so as to measure temperature-dependent optical properties of the sample is also provided. | 12-31-2015 |
20160093755 | Epitaxial Growth of CZT(S,Se) on Silicon - Techniques for epitaxial growth of CZT(S,Se) materials on Si are provided. In one aspect, a method of forming an epitaxial kesterite material is provided which includes the steps of: selecting a Si substrate based on a crystallographic orientation of the Si substrate; forming an epitaxial oxide interlayer on the Si substrate to enhance wettability of the epitaxial kesterite material on the Si substrate, wherein the epitaxial oxide interlayer is formed from a material that is lattice-matched to Si; and forming the epitaxial kesterite material on a side of the epitaxial oxide interlayer opposite the Si substrate, wherein the epitaxial kesterite material includes Cu, Zn, Sn, and at least one of S and Se, and wherein a crystallographic orientation of the epitaxial kesterite material is based on the crystallographic orientation of the Si substrate. A method of forming an epitaxial kesterite-based photovoltaic device and an epitaxial kesterite-based device are also provided. | 03-31-2016 |
Patent application number | Description | Published |
20090011610 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS - A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlO | 01-08-2009 |
20090152642 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 06-18-2009 |
20110165767 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 07-07-2011 |