Patent application number | Description | Published |
20130049190 | METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES - Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material. | 02-28-2013 |
20130113084 | SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER - Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate. | 05-09-2013 |
20130154122 | SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. | 06-20-2013 |
20130256871 | SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS - Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump and to reduce pad parasitic capacitance are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first insulating layer over plural conductor pads of a semiconductor chip and forming an opening over each of the conductor pads. An individual solder structure is coupled to the insulating layer. The solder structure has a projection in each of the openings and in electrical contact with one of the plural conductor pads. | 10-03-2013 |
20130256872 | THERMAL MANAGEMENT OF STACKED SEMICONDUCTOR CHIPS WITH ELECTRICALLY NON-FUNCTIONAL INTERCONNECTS - A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip. | 10-03-2013 |
20130256895 | STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT - A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates. | 10-03-2013 |
20130256913 | DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS - A method of manufacturing is provided that includes forming a first proximity interconnect on a first side of a first semiconductor chip and a first plurality of interconnect structures projecting from the first side. A second proximity interconnect is formed on a second side of a second semiconductor chip and a second plurality of interconnect structures are formed projecting from the second side. The second semiconductor chip is coupled to the first semiconductor chip so that the second side faces the first side and the first interconnect structures are coupled to the second interconnect structures. The first and second proximity interconnects cooperate to provide a proximity interface. The coupling of the first interconnect structures to the second interconnect structures provides desired vertical and lateral alignment of the first and second proximity interconnects. | 10-03-2013 |
20130258610 | SEMICONDUCTOR CHIP DEVICE WITH VENTED LID - Various circuit board lids and methods and using the same are disclosed. In one aspect, an apparatus is provided that includes a lid adapted to cover a semiconductor chip mounted on a circuit board. The lid has a top plate, a first support leg and a second support leg opposite the first support leg adapted to support the lid. The first and second support legs and the top plate define a recess to accommodate the semiconductor chip. The recess has a first opening and a second opening. At least one of the first and second openings extends from the first support leg to the second support leg. | 10-03-2013 |
20130342231 | SEMICONDUCTOR SUBSTRATE WITH ONBOARD TEST STRUCTURE - Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a first test structure onboard an interposer that has a first side and second side opposite the first side. Additional test structures may be fabricated. | 12-26-2013 |
20150049441 | CIRCUIT BOARD WITH CORNER HOLLOWS - A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes. | 02-19-2015 |