Patent application number | Description | Published |
20140286115 | NONVOLATILE RANDOM ACCESS MEMORY - According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command. | 09-25-2014 |
20150063015 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. | 03-05-2015 |
20150063016 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other. | 03-05-2015 |
20150063017 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode. | 03-05-2015 |
20150228320 | NONVOLATILE RANDOM ACCESS MEMORY - According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command. | 08-13-2015 |
20150262631 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells configured to be able to store data; a control circuit configured to control a write operation of data in the memory cell array, and an initialization operation of the memory cell array; and a register control circuit configured to receive a first command including second information for selecting first information relating to control of a cycle of a clock from completion of the write operation of data in the memory cell array to initialization of the memory cell array. | 09-17-2015 |
20160019941 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. | 01-21-2016 |
20160064061 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period. | 03-03-2016 |