Patent application number | Description | Published |
20090269915 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE PREVENTING LOSS OF JUNCTION REGION - A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform. | 10-29-2009 |
20100019386 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 01-28-2010 |
20100052167 | METAL LINE HAVING A MOxSiy/Mo DIFFUSION BARRIER OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line having a Mo | 03-04-2010 |
20100052168 | METAL LINE HAVING A MULTI-LAYERED DIFFUSION LAYER IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line having a multi-layered diffusion layer in a resultant semiconductor device is presented along with corresponding methods of forming the same. The metal line includes an insulation layer, a multi-layered diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The multi-layered diffusion barrier is formed on a surface of the metal line forming region defined in the insulation layer. The diffusion barrier includes a VB | 03-04-2010 |
20100052169 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - An insulation layer is formed on a semiconductor substrate so as to define a metal line forming region. A diffusion barrier having a multi-layered structure of an Mo | 03-04-2010 |
20100052170 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoB | 03-04-2010 |
20110244673 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas. | 10-06-2011 |
20120015516 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 01-19-2012 |
20130093093 | SEMICONDUCTOR DEVICE WITH DAMASCENE BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap. | 04-18-2013 |
20140175659 | SEMICONDUCTOR DEVICE INCLUDING AIR GAPS AND METHOD OF FABRICATING THE SAME - This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs. | 06-26-2014 |
20140179101 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a semiconductor structure having an open portion over a substrate, forming a sacrificial spacer on sidewalls of the open portion, forming a recessed first plug in the open portion, forming an air gap by removing the sacrificial spacer, forming a capping layer to expose the top surface of the recessed first plug and to cap the air gap, forming a protective layer over the capping layer and the recessed first plug, forming an ohmic contact layer over the protective layer, and forming a second plug over the ohmic contact layer. | 06-26-2014 |
20140308794 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion. | 10-16-2014 |
20150014759 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap. | 01-15-2015 |
20150035050 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps. | 02-05-2015 |
20150076693 | SEMICONDUCTOR DEVICE WITH DAMASCENE BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap. | 03-19-2015 |