Patent application number | Description | Published |
20140181118 | METHOD FOR PROCESSING PATENT INFORMATION FOR OUTPUTTING CONVERGENCE INDEX - The present invention relates to a method for outputting a convergence index, and more particularly, to a method for outputting a convergence index by utilizing patent information. According to the method for outputting the convergence index of the present invention, the convergence index can be outputted by using time information related to a patent which is included in a patent group, a patent classification, and an industrial classification that corresponds to the patent classification. The method for outputting the convergence index of the present invention systematically outputs the convergence index by using patent data, which is an objective data, thereby outputting the convergence index which is objective and appropriate. | 06-26-2014 |
20140188739 | METHOD FOR OUTPUTTING CONVERGENCE INDEX - The present invention relates to a method for outputting a convergence index, and more particularly, to a method for outputting a convergence index by utilizing patent information. According to the method for outputting the convergence index of the present invention, the convergence index can be outputted by using time information related to a patent which is included in a patent group, a patent classification, and an industrial classification that corresponds to the patent classification. The method for outputting the convergence index of the present invention systematically outputs the convergence index by using patent data, which is objective data, thereby outputting the convergence index which is objective and appropriate. | 07-03-2014 |
20140195443 | SYSTEM FOR CONVERGENCE INDEX SERVICE - The present invention relates to a system for servicing convergence index, and more particularly, to a system for servicing a convergence index for outputting a convergence index by utilizing patent information and servicing same. According to the system for servicing the convergence index of the present invention, the convergence index can be outputted by using time information related to a patent which is included in a patent group, a patent classification, and an industrial classification that corresponds to the patent classification. The system for servicing the convergence index of the present invention systematically outputs the convergence index by using patent data, which is an objective data, thereby outputting the convergence index which is objective and appropriate. | 07-10-2014 |
20140327844 | TOUCH SCREEN PANEL FOR MULTI-TOUCHING AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing a touch screen panel, including the steps of: forming a spacer array and a mold having a shape corresponding to that of a horizontal groove array or a vertical groove array; fabricating a transparent upper plate having a horizontal groove array including two or more horizontal grooves and a transparent lower plate having a vertical groove array including two or more vertical grooves using the mold; charging a predetermined amount of conductive ink in the horizontal groove array and the vertical groove array; and drying the conductive ink to form a conductive array and then attaching the upper plate to the lower plate. | 11-06-2014 |
Patent application number | Description | Published |
20100327903 | CIRCUIT FOR CALIBRATING IMPEDANCE AND SEMICONDUCTOR APPARATUS USING THE SAME - A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal. | 12-30-2010 |
20110267114 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal. | 11-03-2011 |
20110291713 | SLAVE DEVICE, SYSTEM INCLUDING MASTER DEVICE AND SLAVE DEVICE, METHOD FOR OPERATING THE SAME, AND CHIP PACKAGE - A slave device communicating with a master device includes a transmission unit configured to transmit a signal to the master device through a communication channel, a calibration unit configured to measure a flight time of a calibration signal which is transmitted to the master device and fed back through a calibration channel coupled to the master device, and a transmission delay unit configured to delay the signal transmitted from an internal circuit of the slave device to the transmission unit by a delay value determined according to the measurement result of the calibration unit. | 12-01-2011 |
20130308406 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal. | 11-21-2013 |
20140176192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a differential input unit configured to generate internal differential signals based on external differential signals by using a first level voltage, a signal conversion unit configured to generate an internal synchronization signal based on the internal differential signals in response termination control signals by using a second level voltage, and a duty correction unit configured to correct duty of the internal synchronization signal by using the second level voltage. | 06-26-2014 |