Patent application number | Description | Published |
20100104650 | CHARGED MESOPOROUS SILICA NANOPARTICLE-BASED DRUG DELIVERY SYSTEM FOR CONTROLLED RELEASE AND ENHANCED BIOAVAILABILITY - A charged mesoporous silica nanoparticle (MSN)-based drug delivery system for controlled release and enhanced bioavailability is disclosed. The system comprises a positively charged MSN, which has a silica matrix and an array of pores and/or nanochannels in the matrix. The entire substance of the matrix, all the surfaces and the pores and/or nanochannels comprise a plurality of silanol (Si—OH) and quaternary ammonium functional groups. The bioavailability of a negatively charged bioactive compound can be increased by loading it into the pores and/or nanochannels. The silanol (Si—OH) functional groups on the surfaces lining the walls of the pores and/or nanochannels are free to deprotonate in a fluid having pH above the pI of the positively charged MSN and lead to a sustained release of the negatively charged drug from the pores and/or nanochannels, and thereby enhance the bioavailability of the drug. | 04-29-2010 |
20150099876 | Molecular Catalysts Capable of Catalyzing Oxidation of Hydrocarbons and Method for Oxidizing Hydrocarbons - This invention relates to molecular catalysts and chemical reactions utilizing the same, and particularly to molecular catalysts for efficient catalytic oxidation of hydrocarbons, such as hydrocarbons from natural gas. The molecular catalytic platform provided herein is capable of the facile oxidation of hydrocarbons, for example, under ambient conditions such as near room temperature and atmospheric pressure. | 04-09-2015 |
20160038608 | SILICA-BASED MESOPOROUS CARRIER AND DELIVERY METHOD OF USING THE SAME - Mesoporous carriers for delivering targets into a cell are provided. The mesoporous carriers comprise hollow silica nanospheres (HSN) or mesoporous silica nanoparticles (MSN) and the targets bound to or encapsulated by the hollow silica nanospheres or the mesoporous silica nanoparticles. The targets includes at least two different targets, and the targets may include peptides, proteins, enzymes and/or enzymatic mimetics. | 02-11-2016 |
Patent application number | Description | Published |
20150199258 | CONDITIONAL COMPONENT BREAKPOINT SETTING SYSTEM AND METHOD - A method, computer program product, and computer system for setting, at a computing device, a breakpoint of a plurality of breakpoints for use by a debugger at an entry point of a plurality of entry points for a component of a plurality of components, wherein the breakpoint is set automatically. While executing the debugger on the component, it is determined whether the breakpoint is reached from outside of the component by a program. If the breakpoint is reached from outside of the component, the program executed by the debugger stops. If the breakpoint is reached from inside of the component, the program executed by the debugger continues. | 07-16-2015 |
20150199260 | CONDITIONAL COMPONENT BREAKPOINT SETTING SYSTEM AND METHOD - A method, computer program product, and computer system for setting, at a computing device, a breakpoint of a plurality of breakpoints for use by a debugger at an entry point of a plurality of entry points for a component of a plurality of components, wherein the breakpoint is set automatically. While executing the debugger on the component, it is determined whether the breakpoint is reached from outside of the component by a program. If the breakpoint is reached from outside of the component, the program executed by the debugger stops. If the breakpoint is reached from inside of the component, the program executed by the debugger continues. | 07-16-2015 |
Patent application number | Description | Published |
20110232872 | LIQUID HEAT-DISSIPATING MODULE - The present invention is related to a liquid heat-dissipating module, for dissipating the heat generated by a heating element, at least comprising: a heat-absorbing unit, being connected with the heating element, for absorbing the heat generated by the heating element; a fluid delivery device, for delivering a fluid, the fluid delivery device being stacked with the heat-absorbing unit and having a heat-dissipating structure; and a connecting pipe, being connected with the heat-absorbing unit and the fluid delivery device for delivering the fluid into the heat-absorbing unit, so as to absorb the heat of the heat-absorbing unit; the fluid absorbing the heat is then delivered back to the fluid delivery device, letting the heat-dissipating structure to dissipate the heat contained in the fluid. | 09-29-2011 |
20120176448 | HIGH-SPEED PAGE WIDE PRINTING METHOD AND A PRINTING DEVICE ADAPTIVE TO THE HIGH-SPEED PAGE WIDE PRINTING METHOD - The present invention related to a high-speed page wide printing method, comprising the steps of: providing a printing device and a medium, wherein the printing device at least comprises an ink-jet device including a plurality of odd-number ink-jet nozzles and a plurality of even-number ink-jet nozzles; the printing device receiving a printing order and the ink-jet device executing an ink-jet operation in response to the printing order; and the ink-jet device completing the ink-jet operation for completing a printing operation to a first printing region of the medium. Besides, the odd-number ink-jet nozzle and the adjacent even-number ink-jet nozzle of the ink-jet device form a set and are controlled by the same set of printing control data. Moreover, the ink injected through the plurality of odd-number ink jet nozzle is at least partially overlapped with the ink injected through the adjacent even-number ink-jet nozzle on the medium. | 07-12-2012 |
20120242726 | INK-JET HEAD - The present invention related to an ink-jet head, adaptive for an ink cartridge including at least one ink tank, the ink jet head includes: a nozzle board, having a plurality of nozzles; and an ink-jet chip, being used for controlling the ink-jetting and having a total area region consisting of a length and a width, wherein the total area region includes: a non-wiring region, where at least one ink flow channel being installed therein; and a wiring region, where an internal circuit being installed therein; wherein the internal circuit includes a plurality of ink-jet unit sets, and every ink-jet units of the plurality of ink-jet unit sets include a heater installed correspondingly to the nozzle; wherein the area of the wiring region of the ink-jet chip is less than 77% of the area of the total area region of the ink-jet chip. | 09-27-2012 |
20120242746 | INKJET PRINTHEAD - The present invention related to an inkjet printhead, adaptive for an ink cartridge including three ink-supplying tank, the inkjet printhead includes: a nozzle plate having a plurality of nozzles; and an inkjet chip for controlling ink jetting and having a total area region having a length and a width, the total area region including: a non-wiring region for installing three single ink-supplying flow channels; and a wiring region for installing an internal circuit including a plurality inkjet unit assembly, each inkjet unit of the inkjet unit assembly including a heater installed correspondingly to the nozzle; wherein an area of the wiring region of the inkjet chip is or less than 77% of a total area of the inkjet chip. | 09-27-2012 |
20120242752 | INKJET PRINTHEAD - The present invention related to an inkjet printhead, adaptive for an ink cartridge including one ink-supplying tank, the inkjet printhead includes: a nozzle plate having a plurality of nozzles; and an inkjet chip for controlling ink jetting and having a total area region having a length and a width, the total area region including: a non-wiring region for installing one single ink-supplying flow channels; and a wiring region for installing an internal circuit including a plurality inkjet unit assembly, each inkjet unit of the inkjet unit assembly including a heater installed correspondingly to the nozzle; wherein an area of the wiring region of the inkjet chip is or less than 82% of a total area of the inkjet chip. | 09-27-2012 |
20120242763 | INK-JET HEAD - The present invention related to an ink-jet head, adaptive for an ink cartridge including two ink tanks, the ink-jet head includes: a nozzle board, having a plurality of nozzles; and an ink-jet chip, being used for controlling the ink-jetting and having a total area region consisting of a length and a width, wherein the total area region includes: a non-wiring region, where two ink flow channels being installed therein; and a wiring region, where an internal circuit being installed therein; wherein the internal circuit includes a plurality of ink-jet unit sets, and every ink-jet units of the plurality of ink-jet unit sets include a heater installed correspondingly to the nozzle; wherein the area of the wiring region of the ink-jet chip is less than 77% of the area of the total area region of the ink-jet chip. | 09-27-2012 |
20120287655 | HEAT DISSIPATION DEVICE - The present invention relates to a heat dissipation device, which comprises: a fluid, a fluid delivery device, and a circular pipe. The fluid delivery device is for propelling and delivering the fluid, the circular pipe is connected with the fluid delivery device, at least a portion of the circular pipe itself contacting with a heat generation device for conducting heat to the portion of the circular pipe, so as letting the fluid to be delivered by the fluid delivery device for delivering heat to the rest portion of the circular pipe, and to dissipate the heat generation device. | 11-15-2012 |
Patent application number | Description | Published |
20130328971 | INK-JET PRINTING MODULE - An ink-jet printing module is used for a page-width array ink-jet printer. The ink jet printing module includes a page-width array platen and a plurality of ink-jet cartridges. The page-width array platen has a plurality of receiving cavities arranged as an array. Each of the ink-jet cartridges is detachably and independently embedded into one of the receiving cavities, and includes a body for storing ink, an ink-jet chip to be driven for ejecting the ink, a plurality of nozzles disposed on the ink-jet chip, and a control node for receiving signal to drive the ink-jet chip. The ink-jet chip is disposed on a bottom of the page-width array platen and is driven to eject the ink through the nozzles onto a printing medium. | 12-12-2013 |
20130328972 | INK-JET PRINTING MODULE - An ink-jet printing module is used for a page-width array ink-jet printer. The ink jet printing module includes a page-width array platen and a plurality of ink-jet cartridges. The page-width array platen has a plurality of receiving cavities arranged as an array. Each of the ink-jet cartridges is detachably and independently embedded into one of the receiving cavities. | 12-12-2013 |
20160000139 | THREE-DIMENSIONAL COOKING MACHINE - A three-dimensional cooking machine includes a control computer and a food ingredient laminating device. The control computer is used for previously storing an image file of a desired food model and outputting a control command corresponding to the image file of the food model. The food ingredient laminating device includes an ink-jet printer. The ink-jet printer is controlled to perform a three-dimensional food laminating operation according to the control command from the control computer. | 01-07-2016 |
20160066612 | THREE-DIMENSIONAL FORMING APPARATUS AND METHOD FOR MANUFACTURING MEAT SUBSTITUTE - A three-dimensional meat substitute forming apparatus includes a control computer for previously storing an image file of a meat model and outputting a control command corresponding to the image file of the meat model. The powdery meat substitute material is a powdery non-meat protein food material. A three-dimensional meat substitute forming method includes a pretreating process, a soaking and grinding process, a slurry boiling and filtering process, an atomization drying process, a powder spreading and stratifying process, a printing and solidifying process, a laminating process and an excess powder removing process. Consequently, a three-dimensional meat substitute is produced. | 03-10-2016 |
20160101574 | RAPID PROTOTYPING APPARATUS WITH PAGE-WIDTH ARRAY PRINTING MODULE - A rapid prototyping apparatus with a page-width array printing module is disclosed. The rapid prototyping apparatus includes a construction platform, a movable platform and a page-width array printing module. The construction platform has a construction chamber. The length of the construction chamber is ranged from 0.8 m to 1.5 m, the width of the construction chamber is ranged from 0.8 m to 1.5 m, and the height of construction chamber is ranged from 0.8 m to 1.2 m. The movable platform is disposed above the construction platform. The page-width array printing module is installed on the movable platform and synchronously moved along a single direction in a reciprocating motion. The page-width array printing module has plural inkjet head structures disposed thereon, so that a rapid prototyping width-page printing operation is performed. | 04-14-2016 |
Patent application number | Description | Published |
20140368277 | RADIO FREQUENCY POWER AMPLIFIER AND ELECTRONIC SYSTEM - A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage. | 12-18-2014 |
20150244327 | AMPLIFIER CIRCUIT, BIASING BLOCK WITH OUTPUT GAIN COMPENSATION THEREOF, AND ELECTRONIC APPARATUS - An exemplary embodiment of the present disclosure illustrates an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The a biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing currents are substantially independent to temperature and/or system voltage variation. | 08-27-2015 |
20150280672 | LOW NOISE AMPLIFIER AND RECEIVER - A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a first current and third current. The bias circuit is used for receiving a first current and third current and outputting a first bias voltage and a second bias voltage according to the first current and third current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the first current and third current and further to compensates power gain of the low noise amplifier in order to increase 1 dB gain compression point (P1dB). | 10-01-2015 |
Patent application number | Description | Published |
20140106474 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 04-17-2014 |
20140170782 | SCANNER OVERLAY CORRECTION SYSTEM AND METHOD - A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values. | 06-19-2014 |
20140328534 | DETECTION OF DEFECTS ON WAFER DURING SEMICONDUCTOR FABRICATION - Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to generate a projection. In some embodiments, the non-correctable error image map is transformed via a feature extraction transform such as a Hough transform or a Radon transform. In some embodiments, the projection is compared to a set of rules to identify a signature in the non-correctable error image map indicative of a defect. | 11-06-2014 |
20150015870 | Overlay Abnormality Gating by Z Data - The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process. | 01-15-2015 |
20150027636 | SCANNER OVERLAY CORRECTION SYSTEM AND METHOD - A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values. | 01-29-2015 |
20150081081 | SEMICONDUCTOR FABRICATION COMPONENT RETUNING - Among other things, one or more systems and techniques for retuning a semiconductor fabrication component are provided. The semiconductor fabrication component, such as an advanced process control (APC) component, is configured to evaluate or adjust various fabrication parameters associated with semiconductor fabrication processing. Processing data associated with the semiconductor fabrication component is evaluated to formulate performance indices used to evaluate performance of parameters used by the semiconductor fabrication component. One or more fabrication process change simulations are performed to generate a component operating behavior data structure indicating how different values for the parameters result in improved or degraded performance by the semiconductor fabrication component. In this way, the component operating behavior data structure is evaluated to identify tuning values for the parameters that are used to retune the semiconductor fabrication component. | 03-19-2015 |
20150125970 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 05-07-2015 |
20150162166 | SYSTEM AND METHOD FOR CONTROLLING ION IMPLANTER - A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement. | 06-11-2015 |
20150187662 | METHOD AND/OR SYSTEM FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) - One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector, a spectroscopic signal generator, a comparator, a spectral library, a controller or a CMP device. A spectroscopic signal is generated and is used to determine the thickness of a first material formed on or from a wafer by comparing the spectroscopic signal to a spectral library. Responsive to the thickness not being equal to the desired thickness, the controller instructs the CMP device to perform a rotation to reduce the thickness of the first material. The system and method herein increase the sensitivity of the CMP, such that the thickness of the first material is reduced with greater accuracy and precision, as compared to where the thickness is not measured between consecutive rotations of a wafer. | 07-02-2015 |
20150192616 | Method of Test Probe Alignment Control - A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value. | 07-09-2015 |
20150348797 | Apparatus and Method for Chemical Mechanical Polishing Process Control - An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes. | 12-03-2015 |
Patent application number | Description | Published |
20130298555 | SOLAR-ENERGY HEAT POWER-GENERATING SYSTEM AND THERMOELECTRIC CONVERSION DEVICE THEREOF - A solar-energy heat power-generating system and thermoelectric conversion device thereof, the thermoelectric conversion device comprising a power generator ( | 11-14-2013 |
20140192186 | SOLAR HEAT POWER GENERATION SYSTEM AND DETECTION DEVICE FOR CONDENSER REFLECTING SURFACE THEREOF - A detection device for a condenser reflecting surface of a solar heat power generation system comprises: a horizontal rotary beam disposed above the condenser reflecting surface and capable of rotating in a horizontal surface, a plurality of laser heads being disposed at the bottom end of the horizontal rotary beam, a receiving disk perpendicular to the central axis of the horizontal rotary beam and capable of vertical movement connected at the theoretical focus of the condenser reflecting surface below the horizontal rotary beam, a camera being disposed below the receiving disk. A solar heat power generation system comprises the condenser reflecting surface and the detection device, and the detection device is disposed right above the condenser reflecting surface. | 07-10-2014 |
20150022915 | DISH-TYPE SOLAR CONCENTRATION DEVICE - The present invention discloses a dish-type solar concentration device, comprising a reflection surface, a heat absorber and a dish-type support frame being provided above and below the reflection surface, respectively; further comprising a rigid turntable and a circular orbit fixed onto the ground, the rigid turntable being connected in a rotary manner to the circular orbit through a plurality of bearing wheels, at least one support and one fixed leg being provided on the rigid turntable, a driving mechanism for adjusting an elevation angle of the dish-type support frame being provided on the top end of the support, and the top end of the driving mechanism and the top end of the fixed leg being articulated to the dish-type supporting frame by two first horizontal articulating shafts parallel to each other. By such a structure, the stability and strength of the dish-type solar concentration device can be enhanced. | 01-22-2015 |
Patent application number | Description | Published |
20140104962 | MEMORY, SUPPLY VOLTAGE GENERATION CIRCUIT, AND OPERATION METHOD OF A SUPPLY VOLTAGE GENERATION CIRCUIT USED FOR A MEMORY ARRAY - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 04-17-2014 |
20140204686 | OPERATION METHOD OF A SUPPLY VOLTAGE GENERATION CIRCUIT USED FOR A MEMORY ARRAY - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 07-24-2014 |
20140211573 | MEMORY FOR A VOLTAGE REGULATOR CIRCUIT - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 07-31-2014 |
Patent application number | Description | Published |
20130099852 | CHARGE PUMP CIRCUIT WITH LOW CLOCK FEED-THROUGH - A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit. | 04-25-2013 |
20140146610 | MEMORY AND OPERATION METHOD THEREOF - An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N−M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N−M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided. | 05-29-2014 |
20150095728 | TESTING METHOD FOR REDUCING NUMBER OF OVERKILLS BY REPEATEDLY WRITING DATA TO ADDRESSES IN A NON-VOLATILE MEMORY - A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number. | 04-02-2015 |
20150262621 | Non-Volatile Memory Which Can Increase the Operation Window - A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells. | 09-17-2015 |
Patent application number | Description | Published |
20140376766 | MINIATURE MOVING-COIL SPEAKER - Disclosed is a miniature moving-coil speaker comprising a magnetic circuit system, a vibration system, and an auxiliary system for fixing the magnetic circuit system and the vibration system. The vibration system comprises a diaphragm and a voice coil integrated with the diaphragm. The auxiliary system comprises a plastic enclosure. The diaphragm is installed correspondingly at one end face of the enclosure, while the magnetic circuit system is installed at the other end face of the enclosure opposite the diaphragm; also: a flexible circuit board is arranged on the end face of the enclosure where the magnetic circuit system is installed, and the voice coil is electrically connected to the flexible circuit board. The design reduces product installation height, while at the same time facilitates wire-leading and wire-combing for the miniature moving-coil speaker, and simplifies product design. | 12-25-2014 |
20150036862 | SOUNDER MODULE AND METHOD FOR ASSEMBLING THE SAME - A sounder module, comprising a sounder unit and a casing housing the sounder unit; the sounder unit comprises a magnetic circuit system; the magnetic circuit system comprises a concentrating flux, plate, a magnet and a magnet yoke ( | 02-05-2015 |
20150068027 | ASSEMBLING METHOD FOR MICRO-LOUDSPEAKER ASSEMBLY - Provided is an assembling method for a micro-loudspeaker assembly. The method comprises the steps of: (a) preparing a chuck ring material plate and a vibrating diaphragm material plate, and stamping a number of chuck ring inner holes in the chuck ring material plate; (b) coating an adhesive on the upper surface of the chuck ring material plate stamped with the chuck ring inner holes; (c) bonding the vibrating diaphragm material plate to the upper surface of the chuck ring material plate coated with an adhesive; (d) downwards stamping the part of the vibrating diaphragm material plate corresponding to the chuck ring inner holes into the central part of a vibrating diaphragm; and (e) stamping to form the outer edge of the assembly around the chuck ring inner holes, and removing the assembly from the material plate. | 03-12-2015 |
20150304747 | SPEAKER MODULE - The present invention provides a speaker module comprising a peripheral frame and speaker units housed in the peripheral frame, and the peripheral frame is provided with sound holes in communication with the outside, a front acoustic cavity in communication with the sound holes is defined between one side of the speaker units and the peripheral frame, and a rear acoustic cavity is defined between the peripheral frame and another side of the speaker units away from the front acoustic cavity; in which the speaker units are provided in plurality, and the rear acoustic cavity is divided into the same number of rear sub-cavities as that of the speaker units, and each of the speaker units corresponds to one of the rear sub-cavities and is in communication with its corresponding rear sub-cavity. The above structure makes it easier to adjust the acoustic performance and improves the stereo effect of the product. | 10-22-2015 |