Patent application number | Description | Published |
20110041962 | Spring steel with improved hardenability and pitting resistance - The present invention provides a spring steel that has superior hardenability, undergoes less pitting in a corrosive environment, and can achieve higher stress and toughness. More specifically, the present invention provides a high-strength and high-toughness spring steel with improved hardenability and pitting resistance, containing, in mass percent, 0.40 to 0.70% carbon, 0.05 to 0.50% silicon, 0.60 to 1.00% manganese, 1.00 to 2.00% chromium, 0.010 to 0.050% niobium, 0.005 to 0.050% aluminum, 0.0045 to 0.0100% nitrogen, 0.005 to 0.050% titanium, 0.0005 to 0.0060% boron, no more than 0.015% phosphorus and no more than 0.010% sulfur, the remainder being composed of iron and unavoidable impurities, the steel having a tensile strength of at least 1700 MPa in 400° C. tempering after quenching and a Charpy impact value of at least 40 J/cm | 02-24-2011 |
20120205013 | SPRING STEEL WITH IMPROVED HARDENABILITY AND PITTING RESISTANCE - The present invention provides a spring steel that has superior hardenability, undergoes less pitting in a corrosive environment, and can achieve higher stress and toughness. More specifically, the present invention provides a high-strength and high-toughness spring steel with improved hardenability and pitting resistance, containing, in mass percent, 0.40 to 0.70% carbon, 0.05 to 0.50% silicon, 0.60 to 1.00% manganese, 1.00 to 2.00% chromium, 0.010 to 0.050% niobium, 0.005 to 0.050% aluminum, 0.0045 to 0.0100% nitrogen, 0.005 to 0.050% titanium, 0.0005 to 0.0060% boron, no more than 0.015% phosphorus and no more than 0.010% sulfur, the remainder being composed of iron and unavoidable impurities, the steel having a tensile strength of at least 1700 MPa in 400° C. tempering after quenching and a Charpy impact value of at least 40 J/cm | 08-16-2012 |
Patent application number | Description | Published |
20080265324 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO | 10-30-2008 |
20090000547 | Semiconductor device fabrication method and fabrication apparatus - According to the present invention, there is provided a semiconductor device fabrication method comprising: | 01-01-2009 |
20100159686 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO | 06-24-2010 |
20100173487 | Semiconductor apparatus and method of manufacturing the semiconductor apparatus - A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO | 07-08-2010 |
20110294291 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less. | 12-01-2011 |
20120074504 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device fabrication method includes forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate; forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film; forming a second insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film and forming a second gate electrode sidewall insulating film. | 03-29-2012 |
20130001506 | RESISTANCE CHANGE MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively. | 01-03-2013 |
20130095656 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less. | 04-18-2013 |
20130248966 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges. | 09-26-2013 |
20130341698 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING - According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer. | 12-26-2013 |
20130341699 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, a first charge trap layer on the interface insulating layer, and a second charge trap layer on the first charge trap layer, and a trap level of the second charge trap layer is lower than a trap level of the first charge trap layer. | 12-26-2013 |
20140315378 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING - A nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer. | 10-23-2014 |