Montgomery, Jr.
Bruce Montgomery, Jr., Venice, FL US
Patent application number | Description | Published |
---|---|---|
20110276837 | METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method and system for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a portion of a file and a checksum representing data within the memory block at a first time. Based at least in part on determining that the memory block is mapped to the same portion of the same file at a second time, it is indicated that the checksum represents expected data within the memory block. A system for verifying memory device integrity is also disclosed. | 11-10-2011 |
20110276844 | METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is designated read-only. A current checksum is calculated based at least in part on data within the memory block. When the first memory block is designated read-only, and the prior checksum represents expected data within the first memory block, it is determined whether the current checksum is equal to the prior checksum. When the current checksum is not equal to the prior checksum, a verification failure for the first memory block is indicated via a notification interface. A system for verifying memory device integrity is also disclosed. | 11-10-2011 |
20120144151 | METHODS AND SYSTEM FOR ENSURING MEMORY DEVICE INTEGRITY - A method for protecting memory segments of a memory device is provided. The method includes receiving, by a processor coupled to the memory device, a request to allocate memory from an application, being executed by the processor, wherein the request includes a requested memory size and allocating, by the processor, a portion of memory having a size greater than the requested memory size. The method also includes creating, by the processor, a permitted read counter associated with the allocated portion of memory, wherein the permitted read counter is initialized to an initial value, and determining, by the processor, whether access to the memory segment is permitted using the permitted read counter. A system for protecting memory segments of a memory device is also disclosed. | 06-07-2012 |
20120159085 | METHODS AND SYSTEM FOR VERIFYING MEMORY DEVICE INTEGRITY - A method for validating an eligibility for verification of a memory device within an embedded demand paged memory operating system environment is provided. The method includes receiving a request from an application being executed by a processor coupled to the memory device, the request to utilize at least one memory location. The method includes identifying, by the processor, at least one memory block corresponding to at least one memory location within the memory device, determining, by the processor, whether the at least one memory block is eligible for verification, and producing an eligibility result based on the determination by the processor. A system for validating an eligibility for verifying memory device integrity is also disclosed. | 06-21-2012 |
Bruce Ray Montgomery, Jr., Bradenton, FL US
Patent application number | Description | Published |
---|---|---|
20110043367 | INTELLIGENT NOTIFICATION APPLIANCE CIRCUIT AND SYSTEM - An intelligent notification appliance circuit has a controller and one or more addressable notification appliances coupled with a single pair of wires. The controller outputs integrated power, audio and control signals, and transmits the integrated signals to the one or more addressable notification appliances. Thus, the one or more addressable notification appliances are powered, operated, controlled, and monitored using the intelligent notification appliance circuit. When the intelligent notification appliance circuit is implemented in a fire and/or mass notification system, that system is able to provide integrated audio signals, power signals and control signals over a single pair of wires. The integrated audio signals may carry data indicative of live or recorded music and/or voice messages, such as: mass notification messages, general page, voice evacuation, and the like. | 02-24-2011 |
Erwin B. Montgomery, Jr., Middleton, WI US
Patent application number | Description | Published |
---|---|---|
20090043220 | METHODS AND DEVICES FOR ANALYSIS OF CLUSTERED DATA, IN PARTICULAR ACTION POTENTIALS (I.E. NEURON FIRING SIGNALS IN THE BRAIN) - Methods for clustering of multi-dimensional data allow unsupervised grouping of multi-dimensional data points into clusters having like characteristics. The methods may be usefully applied to extracellular action potentials (neuronal spikes) measured from the brain, whereby spike data may be grouped in accordance with dimensions such as spike period, spike shape, etc., to assist in identification and location of individual neurons and/or regions of the brain. | 02-12-2009 |
20090125080 | INTRAVENTRICULAR ELECTRODES FOR ELECTRICAL STIMULATION OF THE BRAIN - An electrode—preferably an anode (current sink)—is implanted within a ventricle of the brain so that the cerebrospinal fluid therein, which is highly conductive, effectively makes the ventricle a conductive extension of the anode. An opposing electrode (i.e., a cathode) can then be situated within or outside the brain (e.g., extradurally) so that a portion of the brain to be electrically stimulated is situated between the electrodes. The electrodes can then be energized at appropriate frequencies and current/voltage levels to apply the desired stimulation, in a manner similar to preexisting Deep Brain Stimulation (DBS), Extradural Motor Cortex Stimulation (EMCS), and other electrical brain stimulation procedures. | 05-14-2009 |
George Paul Montgomery, Jr., Beverly Hills, MI US
Patent application number | Description | Published |
---|---|---|
20100228423 | AGGREGATED INFORMATION FUSION FOR ENHANCED DIAGNOSTICS, PROGNOSTICS AND MAINTENANCE PRACTICES OF VEHICLES - A system and method for enhancing vehicle diagnostic and prognostic algorithms and improving vehicle maintenance practices. The method includes collecting data from vehicle components, sub-systems and systems, and storing the collected data in a database. The collected and stored data can be from multiple sources for similar vehicles or similar components and can include various types of trouble codes and labor codes as well as other information, such as operational data and physics of failure data, which are fused together. The method generates classes for different vehicle components, sub-systems and systems, and builds feature extractors for each class using data mining techniques of the data stored in the database. The method also generates classifiers that classify the features for each class. The feature extractors and feature classifiers are used to determine when a fault condition has occurred for a vehicle component, sub-system or system. | 09-09-2010 |
20110172874 | FAULT PREDICTION FRAMEWORK USING TEMPORAL DATA MINING - A vehicle fault diagnosis and prognosis system includes a computing platform configured to receive a classifier from a remote server, the computing platform tangibly embodying computer-executable instructions for evaluating data sequences received from a vehicle control network and applying the classifier to the data sequences, wherein the classifier is configured to determine if the data sequences define a pattern that is associated with a particular fault. | 07-14-2011 |