Mohana
Mohana Dhamayanthi, Singapore SG
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20090040987 | APPARATUS FOR REDUCING SIGNALLING DATA BURSTS IN MOBILE NETWORK - A technology is disclosed for reducing the burst of DAD messages which may be triggered due to the change of the network prefix when using the technique of the neighbor discovery proxy. According to this technology, in roaming from the access network link | 02-12-2009 |
Mohana Jeyatharan, Singapore SG
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20100238864 | MOBILE TERMINAL, NETWORK NODE, AND PACKET TRANSFER MANAGEMENT NODE - A technique is disclosed, according to which a race condition between a PMIPv6 binding by a PBU message of PMIPv6 and a CMIPv6 binding by a BU message of CMIPv6 can be resolved. MN | 09-23-2010 |
Mohana Lingappa, Baltimore, MD US
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20110165223 | Antitumor Immunization by Liposomal Delivery of Vaccine to the Spleen - The present invention relates to methods for preventing, reducing or treating a variety of conditions, including cancer, and vaccines, compositions and liposomes used to elicit or amplify an immune response specific to the condition by delivering to the spleen of an individual a pegylated liposome construct having a diameter of greater than about 300 nm and including a therapeutic agent and an adjuvant for eliciting or amplifying the immune response. | 07-07-2011 |
Mohana Posam, Sunnyvale, CA US
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20130117553 | Method and Apparatus for Increasing the Output of a Cryptographic System - The rate at which packets are provided to a cryptographic engine of a cryptographic system is adjusted using a feedback mechanism to increase the output of the cryptographic system. Data is classified and queued on a per class/flow basis and stored in input queues prior to being processed. A class based queue scheduler is implemented to select data from the input queues to be transmitted to the cryptographic engine. The cryptographic engine operates in processing cycles. At each cycle, an amount of data is transferred from the input queues to a cryptographic engine input queue. A cryptographic accelerator in the cryptographic engine processes the data on the cryptographic engine input queue during the cycle. The output rate of the cryptographic accelerator is measured during the cycle and this value is used as feedback to determine how much data should be passed to the cryptographic engine for a subsequent cycle. | 05-09-2013 |
Mohana Tandyala, Fremont, CA US
Patent application number | Description | Published |
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20150378682 | EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation. | 12-31-2015 |
20150379164 | MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks. | 12-31-2015 |