Patent application number | Description | Published |
20120242346 | Power Compensation in 3DIC Testing - A device, such as a 3DIC stacked device includes a first device under test (DUT) connected to a first force pad by a first through substrate via (TSV) stack and connected to a first sense pad by a second TSV stack. The device further includes a second DUT stacked above the first DUT and connected to a second force pad and a second force pad by a second third TSV and connected to a second sense pad by a fourth TSV. Functional blocks on either the first or second blocks can be accessed for testing by way of the TSVs. In some applications the TSVs are vertically aligned to form TSV stacks. | 09-27-2012 |
20120246514 | Adaptive Test Sequence for Testing Integrated Circuits - A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence. | 09-27-2012 |
20120256649 | Dynamic Testing Based on Thermal and Stress Conditions - A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results. | 10-11-2012 |
20120286814 | 3D IC Testing Apparatus - A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once. | 11-15-2012 |
20130015872 | Test Schemes and Apparatus for Passive InterposersAANM Lee; Yun-HanAACI Baoshan TownshipAACO TWAAGP Lee; Yun-Han Baoshan Township TWAANM Wang; Mill-JerAACI Hsin-ChuAACO TWAAGP Wang; Mill-Jer Hsin-Chu TWAANM Chou; Tan-LiAACI Zhubei CityAACO TWAAGP Chou; Tan-Li Zhubei City TW - A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern. | 01-17-2013 |
20130078745 | Production Flow and Reusable Testing Method - An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card. | 03-28-2013 |
20130099812 | Probe Cards for Probing Integrated Circuits - A device includes a probe card, which further includes a chip. The chip includes a semiconductor substrate, a test engine disposed in the chip, wherein the test engine comprises a device formed on the semiconductor substrate, wherein the device is selected from the group consisting essentially of a passive device, an active device, and combinations thereof. A plurality of probe contacts is formed on a surface of the chip and electrically connected to the test engine. | 04-25-2013 |
20130147049 | Circuit Probing Structures and Methods for Probing the Same - A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component. | 06-13-2013 |
20140176165 | Apparatus for Three Dimensional Integrated Circuit Testing - A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit. | 06-26-2014 |
20140361804 | METHOD AND APPARATUS OF WAFER TESTING - A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies. | 12-11-2014 |
20150087089 | 3D IC Testing Apparatus - A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup. | 03-26-2015 |