Patent application number | Description | Published |
20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 12-10-2009 |
20100207281 | Semiconductor Chip with Reinforcement Layer - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. | 08-19-2010 |
20100301460 | SEMICONDUCTOR DEVICE HAVING A FILLED TRENCH STRUCTURE AND METHODS FOR FABRICATING THE SAME - Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate. | 12-02-2010 |
20110031603 | SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. | 02-10-2011 |
20130221517 | SEMICONDUCTOR WORKPIECE WITH BACKSIDE METALLIZATION AND METHODS OF DICING THE SAME - Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip. | 08-29-2013 |
20130256872 | THERMAL MANAGEMENT OF STACKED SEMICONDUCTOR CHIPS WITH ELECTRICALLY NON-FUNCTIONAL INTERCONNECTS - A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip. | 10-03-2013 |
20130256895 | STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT - A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates. | 10-03-2013 |
20130256913 | DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS - A method of manufacturing is provided that includes forming a first proximity interconnect on a first side of a first semiconductor chip and a first plurality of interconnect structures projecting from the first side. A second proximity interconnect is formed on a second side of a second semiconductor chip and a second plurality of interconnect structures are formed projecting from the second side. The second semiconductor chip is coupled to the first semiconductor chip so that the second side faces the first side and the first interconnect structures are coupled to the second interconnect structures. The first and second proximity interconnects cooperate to provide a proximity interface. The coupling of the first interconnect structures to the second interconnect structures provides desired vertical and lateral alignment of the first and second proximity interconnects. | 10-03-2013 |