Patent application number | Description | Published |
20080209289 | PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME - An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank. | 08-28-2008 |
20080222464 | Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test - A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester. | 09-11-2008 |
20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 10-16-2008 |
20090115447 | Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit - A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state. | 05-07-2009 |
20090144673 | PARTIAL GOOD SCHEMA FOR INTEGRATED CIRCUITS HAVING PARALLEL EXECUTION UNITS - Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm. | 06-04-2009 |
20090154269 | MANAGING REDUNDANT MEMORY IN A VOLTAGE ISLAND - An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers. | 06-18-2009 |
20090161722 | AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK - A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state. | 06-25-2009 |
20090180584 | DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA - The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register. | 07-16-2009 |
20090217116 | DIAGNOSABLE GENERAL PURPOSE TEST REGISTERS SCAN CHAIN DESIGN - A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L | 08-27-2009 |
20090249146 | AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-TEST (ABIST) CIRCUITRY - A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree. | 10-01-2009 |
20090251169 | INTEGRATION OF LBIST INTO ARRAY BISR FLOW - A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality. | 10-08-2009 |
20090251978 | INTEGRATION OF LBIST INTO ARRAY BISR FLOW - A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality. | 10-08-2009 |
20090302889 | INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK - Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector. | 12-10-2009 |
20090307637 | METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK - Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit. | 12-10-2009 |
20090319818 | METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins. | 12-24-2009 |
20090319841 | STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal. | 12-24-2009 |
20110113280 | CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR - A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed. | 05-12-2011 |
20120062300 | CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY - Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design. | 03-15-2012 |
20120176144 | AT-SPEED SCAN ENABLE SWITCHING CIRCUIT - A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations. | 07-12-2012 |
20130031319 | INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING OPERATIONS IN SINGLE FUSEBAY ARCHITECTURE - An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data. | 01-31-2013 |
20130033951 | STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY - Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended. | 02-07-2013 |
20130042166 | FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD - Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention. | 02-14-2013 |
20130058176 | DETERMINING FUSEBAY STORAGE ELEMENT USAGE - Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included. | 03-07-2013 |
20130139010 | CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR - A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed. | 05-30-2013 |
20130181838 | SECURITY-ENHANCED RADIO FREQUENCY OBJECT LOCATOR SYSTEM, METHOD AND PROGRAM STORAGE DEVICE - Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user. | 07-18-2013 |
20130185684 | INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM - Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit. | 07-18-2013 |
20130205268 | VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION - Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks. | 08-08-2013 |
20130272072 | BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES - Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed. | 10-17-2013 |
20130275821 | READ ONLY MEMORY (ROM) WITH REDUNDANCY - A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices. | 10-17-2013 |
20140040685 | BUILT-IN-SELF-TEST (BIST) ORGANIZATIONAL FILE GENERATION - Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file. | 02-06-2014 |
20140129888 | STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES - Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected. | 05-08-2014 |
20140143619 | MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC - Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied. | 05-22-2014 |
20140149810 | SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY - In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing. | 05-29-2014 |
20140189448 | DECREASING POWER SUPPLY DEMAND DURING BIST INITIALIZATIONS - Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal. | 07-03-2014 |
20140258797 | BUILT-IN-SELF-TEST (BIST) TEST TIME REDUCTION - Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data. | 09-11-2014 |
20140351662 | READ ONLY MEMORY (ROM) WITH REDUNDANCY - A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices. | 11-27-2014 |
20150039950 | APPARATUS FOR CAPTURING RESULTS OF MEMORY TESTING - A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory. | 02-05-2015 |
20150070048 | VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES - Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit. | 03-12-2015 |