Patent application number | Description | Published |
20150156141 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device includes a splitter in which an input stream made up of a plurality of packets is split, so as to generate split streams of a plurality of channels, of which the smallest increment is base band frames (BBFs) where the packets of the input stream are placed in consecutive order in a data field of the BBF which is the object of forward error correction (FEC). | 06-04-2015 |
20150237175 | TRANSMISSION APPARATUS, TRANSMISSION METHOD, RECEPTION APPARATUS, AND RECEPTION METHOD - The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method which make it possible to control redundancy of a header in packet communication. A region representing a packet length in a header of a packet is switched and set according to a size of a payload of an input packet. That is, according to the packet length, switching between a short packet mode to represent the packet length only by five bits of a packet length part FH | 08-20-2015 |
20150358659 | BROADCAST TRANSITION CHANNEL - A distribution system and reception apparatus, and methods thereof, are provided for broadcasting and receiving a plurality of first services from a plurality of different broadcast providers, which broadcast a plurality of second services over a plurality of different broadcast channels, on a transition broadcast channel that is different from the plurality of different broadcast channels. The system includes at least one receiver and a transmitter. The at least one receiver is configured to receive the plurality of first services from the plurality of different broadcast providers. The transmitter is configured to broadcast the plurality of first services over the transition broadcast channel. | 12-10-2015 |
20160049960 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b | 02-18-2016 |
20160065244 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b | 03-03-2016 |
20160072523 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code. | 03-10-2016 |
20160079998 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. In the interchanging, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b | 03-17-2016 |