Patent application number | Description | Published |
20090196086 | HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM - A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set. | 08-06-2009 |
20100117242 | TECHNIQUE FOR PACKAGING MULTIPLE INTEGRATED CIRCUITS - A semiconductor device includes an intermediate substrate having a first surface and a second surface, a first die attached to the first surface of the intermediate substrate. The first die has a first active surface, and the first active surface faces the intermediate substrate. A second die is attached to the second surface of the intermediate substrate, has a second active surface, faces the intermediate substrate, and is coupled to the first die through an electrically conductive material in the intermediate substrate. An organic material encapsulates at least an edge of the intermediate substrate. There is also a method of forming the semiconductor device. | 05-13-2010 |
20110057306 | EDGE MOUNTED INTEGRATED CIRCUITS WITH HEAT SINK - A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circuits having ports on the second edge. The second edges are connected to the substrate. The first major surface of the second integrated circuit is parallel with the second major surface of the first integrated circuit. The heat sink has a backplane adjacent to the third edge, a first portion along the first major surface of the first integrated circuit, a second portion along the second major surface of the second integrated circuit extending from the backplane, and an insert between the first major surface of the second integrated circuit and the second major surface of the first integrated circuit. | 03-10-2011 |
20110108965 | SEMICONDUCTOR DEVICE PACKAGE - A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings | 05-12-2011 |
20120020040 | Package-to-package stacking by using interposer with traces, and or standoffs and solder balls - The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack. | 01-26-2012 |
20130087926 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device. | 04-11-2013 |
20130088255 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device. | 04-11-2013 |
20130181350 | SEMICONDUCTOR DEVICES WITH NONCONDUCTIVE VIAS - An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures. | 07-18-2013 |
20130320480 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES - A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate. | 12-05-2013 |
20140001641 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES | 01-02-2014 |
20140071652 | TECHNIQUES FOR REDUCING INDUCTANCE IN THROUGH-DIE VIAS OF AN ELECTRONIC ASSEMBLY - An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly. | 03-13-2014 |
20140197541 | MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE - A microelectronic assembly ( | 07-17-2014 |
20140252487 | Gate Security Feature - An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., | 09-11-2014 |
20140362425 | Communication System Die Stack - A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks ( | 12-11-2014 |
20140363119 | Integration of a MEMS Beam with Optical Waveguide and Deflection in Two Dimensions - A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g., | 12-11-2014 |
20140363120 | Optical Backplane Mirror - An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer ( | 12-11-2014 |
20140363124 | Optical Redundancy - A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a first integrated circuit link element ( | 12-11-2014 |
20140363153 | Optical Die Test Interface - An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures ( | 12-11-2014 |
20140363172 | Die Stack with Optical TSVs - A high density, low power, high performance information system, method and apparatus are described in which a laser source ( | 12-11-2014 |
20140363905 | Optical Wafer and Die Probe Testing - An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die ( | 12-11-2014 |
20150008567 | USING AN INTEGRATED CIRCUIT DIE CONFIGURATION FOR PACKAGE HEIGHT REDUCTION - A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface. | 01-08-2015 |
20150061097 | EDGE COUPLING OF SEMICONDUCTOR DIES - Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together. | 03-05-2015 |