Patent application number | Description | Published |
20130043505 | APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed. | 02-21-2013 |
20140160851 | APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS - Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described. | 06-12-2014 |
20140203344 | 3D MEMORY - Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension. | 07-24-2014 |
20140264447 | APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed. | 09-18-2014 |
Patent application number | Description | Published |
20080257714 | METHOD OF MAKING A TMR SENSOR HAVING A TUNNEL BARRIER WITH GRADED OXYGEN CONTENT - A method for manufacturing a tunnel junction magnetoresistive sensor having improved magnetic performance and reliability. The method includes depositing a Mg—O barrier layer in a sputter deposition tool in a chamber having an oxygen concentration that changes. For example, the sputter deposition could be initiated with a first oxygen concentration in the chamber, and then, during the deposition of the barrier layer the oxygen concentration can be reduced. | 10-23-2008 |
20080285182 | ENHANCED ANTI-PARALLEL-PINNED SENSOR USING THIN RUTHENIUM SPACER AND HIGH MAGNETIC FIELD ANNEALING - An anti-parallel pinned sensor is provided with a spacer that increases the anti-parallel coupling strength of the sensor. The anti-parallel pinned sensor is a GMR or TMR sensor having a pure ruthenium or ruthenium alloy spacer. The thickness of the spacer is less than 0.8 nm, preferably between 0.1 and 0.6 nm. The spacer is also annealed in a magnetic field that is 1.5 Tesla or higher, and preferably greater than 5 Tesla. This design yields unexpected results by more than tripling the pinning field over that of typical AP-pinned GMR and TMR sensors that utilize ruthenium spacers which are 0.8 nm thick and annealed in a relatively low magnetic field of approximately 1.3 Tesla. | 11-20-2008 |
20090165286 | METHOD FOR MANUFACTURING AN ULTRA NARROW GAP MAGNETORESISTIVE SENSOR - A method for manufacturing a magnetoresistive sensor that decreases the stack height of the sensor. The method includes forming a sensor structure having at its top, a Ru layer and a Ta layer over the Ru layer. An annealing process is performed to set the magnetization of the pinned layer of the sensor structure. After the annealing process has been completed and the Ta layer is no longer needed, an ion milling process is performed to remove the Ta layer. | 07-02-2009 |
20090168254 | Test device and method for measurement of tunneling magnetoresistance properties of a manufacturable wafer by the current-in-plane-tunneling technique - A combined manufacturable wafer and test device for measuring a tunneling-magnetoresistance property of a tunneling-magnetoresistance, sensor-layer structure. The combined manufacturable wafer and test device comprises a tunneling-magnetoresistance, sensor-layer structure disposed on a substrate. The combined manufacturable wafer and test device also comprises a plurality of partially fabricated tunneling-magnetoresistance sensors; at least one of the partially fabricated tunneling-magnetoresistance sensors is disposed at one of a plurality of first locations. The test device is disposed on the substrate at a second location different from the plurality of first locations. The test device allows measurement of the tunneling-magnetoresistance property of the tunneling-magnetoresistance, sensor-layer structure using a current-in-plane-tunneling technique. | 07-02-2009 |
20090168256 | MAGNETORESISTANCE (MR) READ ELEMENTS HAVING AN ACTIVE SHIELD - Read elements and associated methods of fabrication are disclosed. A read element as described herein includes a magnetoresistance (MR) sensor sandwiched between first and second shields. The read element uses the first shield as an active portion of the MR sensor. Instead of implementing an AFM pinning layer in the MR sensor, the first shield takes the place of the AFM pinning layer. The first shield is orthogonally coupled to the pinned layer through an orthogonal coupling layer, such as a thin layer of AFM material. Through this structure, the magnetic moment of the first shield pins the magnetic moment of the pinned layer transverse to the ABS of the read element, and an AFM pinning layer is not needed. | 07-02-2009 |
20090168271 | DUAL-LAYER FREE LAYER IN A TUNNELING MAGNETORESISTANCE (TMR) ELEMENT HAVING DIFFERENT MAGNETIC THICKNESSES - Tunneling magnetoresistive (TMR) elements and associated methods of fabrication are disclosed. In one embodiment, the TMR element includes a ferromagnetic pinned layer structure, a tunnel barrier layer, and a free layer structure comprised of dual-layers. The free layer structure includes a first free layer and a second amorphous free layer. The magnetic thicknesses of the first free layer and the second amorphous free layer of the dual layer structure differ to provide improved TMR performance. In one example, the first free layer may have a magnetic thickness that is less than 40% of the total magnetic thickness of the free layer structure. | 07-02-2009 |
20090257149 | MAGNETORESISTIVE SENSOR WITH SUB-LAYERING OF PINNED LAYERS - Methods and apparatus provide magnetoresistance sensors. A tunneling magnetoresistance (TMR) sensor may include configurations that are arranged as a top TMR stack. One of two antiparallel layers of pinned layers within the TMR stack may be subdivided by a spacer layer. Tantalum may form the spacer layer that is inserted in a reference layer, which is one of the pinned layers and is located between a barrier layer and an antiparallel coupling layer that enables antiparallel coupling between the reference layer and a keeper layer of the pinned layers. The barrier layer deposited on a free layer of the TMR stacks separates the pinned layers from the free layer such that TMR effects are detectable with the sensors. | 10-15-2009 |
20130257421 | METHOD AND SYSTEM FOR PERFORMING ON-WAFER TESTING OF HEADS - A method and system for testing a read transducer are described. The read transducer includes a read sensor fabricated on a wafer. A system includes a test structure that resides on the wafer. The test structure includes a test device and a heater. The test device corresponds to the read sensor. The heater is in proximity to the test device and is configured to heat the test device substantially without heating the read sensor. Thus, the test structure allows for on-wafer testing of the test device at a plurality of temperatures above an ambient temperature. | 10-03-2013 |