Patent application number | Description | Published |
20110304048 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential. | 12-15-2011 |
20140159663 | BATTERY CONTROL CIRCUIT - A battery module includes an anode terminal, a cathode terminal, and multiple capacitor cells. Multiple tap electrodes are each provided to a corresponding connection node that connects adjacent capacitor cells. An intermediate terminal is connected to one from among the multiple tap electrodes. A battery control circuit includes a cell balance circuit configured to stabilize each of the voltages at the multiple tap electrodes to a corresponding target voltage level. The voltage at the anode terminal is supplied to the power supply terminal of the cell balance circuit. | 06-12-2014 |
20140175880 | ENERGY HARVESTING APPARATUS AND ENERGY HARVESTING SYSTEM - An energy harvesting apparatus includes: a capacitor configured to store energy generated by an energy harvesting element; and a switch connected to the capacitor and configured to switch energy supply from the capacitor to a load based on a capacitor voltage with which the capacitor is charged. An energy harvesting system includes: energy harvesting elements; energy harvesting apparatuses which are provided to respectively correspond to the energy harvesting elements; and a load as an energy supply destination connected to the energy harvesting apparatuses. | 06-26-2014 |
20140300007 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential. | 10-09-2014 |
20140320071 | ELECTRICAL STORAGE DEVICE MONITORING CIRCUIT, CHARGING SYSTEM, AND INTEGRATED CIRCUIT - An electrical storage device monitoring circuit includes a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the current electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit. | 10-30-2014 |
Patent application number | Description | Published |
20090166620 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 07-02-2009 |
20100327324 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 12-30-2010 |
20140246703 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell. | 09-04-2014 |
Patent application number | Description | Published |
20080238481 | LEVEL SHIFT CIRCUIT - In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W | 10-02-2008 |
20100134193 | OSCILLATION CIRCUIT - An oscillation circuit according to the present invention comprises a solid-state oscillator, an amplifier for feedback-controlling the solid-state oscillator, and ESD protecting circuits respectively connected to the input and output sides of the amplifier, wherein the ESD protecting circuit on the input side of the amplifier comprises an ESD protecting element whose constituent is a diode having a P-type diffusion layer and an N-type diffusion layer, and the ESD protecting circuit on the output side of the amplifier comprises an ESD protecting element whose constituent is an MOS transistor. | 06-03-2010 |
20100230725 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell. | 09-16-2010 |
Patent application number | Description | Published |
20090086135 | Liquid Crystal Display Device - (Object) To provide a liquid crystal display device where the aperture ratio of pixels is higher.
| 04-02-2009 |
20090237342 | Liquid crystal display device - A liquid crystal display device which can enhance a numerical aperture is provided. In a so-called IPS-method liquid crystal display device, the pixel electrode is formed of a transparent conductive film having a planar shape which is formed in each pixel region on a first insulation film formed on the first substrate to cover the gate signal line, the counter electrode is formed of a transparent conductive film including plural linear portions arranged parallel to each other and a frame portion connecting end portions of the linear portions to each other, the transparent conductive film of the counter electrode being formed on a second insulation film formed on the first substrate to cover the pixel electrode, and the plurality of linear portions of the counter electrode being arranged on the pixel electrode in an overlapping manner, and assuming two pixels which are arranged adjacent to each other with the gate signal line formed as a boundary therebetween as a first pixel and a second pixel respectively, a gate-signal-line side of the pixel electrode of the first pixel is formed on a first-pixel side of the gate signal line in an overlapping manner, and a gate-signal-line side of the pixel electrode of the second pixel is formed on a second-pixel side of the gate signal line in an overlapping manner, and the gate-signal-line-side frame portion of the counter electrode of the first pixel and the gate-signal-line-side frame portion of the counter electrode of the second pixel are formed in common on the gate signal line in a striding manner. | 09-24-2009 |
20090295700 | Display Device - A display device includes a display region which is constituted of a plurality of partial regions, and drive circuits which are connected to a plurality of video signal lines for respective partial regions. The video signal lines and the drive circuits are connected with each other via relay lines. A center line of the drive circuit and a center line of the partial region are arranged at positions displaced from each other, and the relay lines have a bent portion between the drive circuit and the video signal lines. By forming the bent portion on the relay line, the line resistances of the relay lines can be adjusted thus decreasing display irregularities generated by the positional displacement of the drive circuit. | 12-03-2009 |
20100053536 | LIQUID CRYSTAL DISPLAY DEVICE - The liquid crystal display device is provided with a plurality of spacers and a plurality of pedestals which include a first group of the spacers and the pedestals, the first group including at least a pair of one of the spacers and one of the pedestals opposing to each other, and a second group of the spacers and the pedestals, the second group including at least another pair of another one of the spacers and another one of the pedestals opposing to each other, in which the pair of the spacer and the pedestal which form the first group and the pair of the spacer and the pedestal which form the second group are disposed so that a center of the first surface and a center of the second surface are displaced in different directions. | 03-04-2010 |
20120268358 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device is provided which can enhance a numerical aperture. The display has a pixel transparent conductive film electrode and a transparent conductive film counter electrode formed on an insulation film, which in turn is formed on a first substrate to cover the pixel electrode. A plurality of linear portions of the counter electrode are arranged on the pixel electrode. A gate-signal-line side of the pixel electrode of the first pixel is formed on a first-pixel side of the gate signal line and a gate-signal-line side of the pixel electrode of the second pixel is formed on a second-pixel side of the gate signal line. The gate-signal-line-side frame portion of the counter electrode of the first pixel and the gate-signal-line-side frame portion of the counter electrode of the second pixel are formed in common on the gate signal line in a striding manner. | 10-25-2012 |
20130286337 | LIQUID CRYSTAL DISPLAY DEVICE - The liquid crystal display device is provided with a plurality of spacers and a plurality of pedestals which include a first group of the spacers and the pedestals, the first group including at least a pair of one of the spacers and one of the pedestals opposing to each other, and a second group of the spacers and the pedestals, the second group including at least another pair of another one of the spacers and another one of the pedestals opposing to each other, in which the pair of the spacer and the pedestal which form the first group and the pair of the spacer and the pedestal which form the second group are disposed so that a center of the first surface and a center of the second surface are displaced in different directions. | 10-31-2013 |