Patent application number | Description | Published |
20080203427 | SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE - A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover. | 08-28-2008 |
20080203486 | METHOD FOR DIFFERENTIAL SPACER REMOVAL BY WET CHEMICAL ETCH PROCESS AND DEVICE WITH DIFFERENTIAL SPACER STRUCTURE - By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions. | 08-28-2008 |
20080237723 | METHOD FOR CREATING TENSILE STRAIN BY REPEATEDLY APPLIED STRESS MEMORIZATION TECHNIQUES - By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain. | 10-02-2008 |
20090001479 | TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME - By removing an upper portion of a complex spacer structure, such as a triple spacer structure, an upper surface of an intermediate spacer element may be exposed, thereby enabling the removal of the outermost spacer and a material reduction of the intermediate spacer in a well-controllable common etch process. Consequently, sidewall portions of the gate electrode may be efficiently exposed for a subsequent silicidation process, while the residual reduced spacer provides sufficient process margins. Thereafter, highly stressed material may be deposited, thereby providing an enhanced stress transfer mechanism. | 01-01-2009 |
20090085652 | COMPENSATION OF OPERATING TIME RELATED DEGRADATION OF OPERATING SPEED BY ADAPTING THE SUPPLY VOLTAGE - By controlled increase of the supply voltage of sophisticated integrated circuits, the performance degradation over a lifetime may be significantly reduced. For this purpose, the upper limits of the supply voltage and the thermal design power are taken into consideration when increasing the supply voltage, which may then compensate for a typical performance degradation resulting in a more stable overall performance of integrated circuits. Thus, greatly reduced guard bands for parts classification may be used compared to conventional strategies. | 04-02-2009 |
20090111223 | SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY - By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques. | 04-30-2009 |
20090142900 | METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS - By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps. | 06-04-2009 |
20090246927 | INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE - By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors. | 10-01-2009 |
20090295457 | COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE - Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures. | 12-03-2009 |
20100025743 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED BORON CONFINEMENT - By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like. | 02-04-2010 |
20100078736 | ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. | 04-01-2010 |
20100109757 | COMPENSATION OF OPERATING TIME-RELATED DEGRADATION OF OPERATING SPEED BY A CONSTANT TOTAL DIE POWER MODE - By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage. | 05-06-2010 |
20100134167 | COMPENSATION OF DEGRADATION OF PERFORMANCE OF SEMICONDUCTOR DEVICES BY CLOCK DUTY CYCLE ADAPTATION - The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required. | 06-03-2010 |
20100219474 | TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE - A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure. | 09-02-2010 |
20100219719 | STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL - An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain. | 09-02-2010 |
20100244107 | REDUCING SILICIDE RESISTANCE IN SILICON/GERMANIUM-CONTAINING DRAIN/SOURCE REGIONS OF TRANSISTORS - In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon layer may be formed on the silicon/germanium alloy, possibly including a further strain-inducing atomic species other than germanium, in order to provide a high strain component while also providing superior conditions during the silicidation process. | 09-30-2010 |
20100327358 | SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL - The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material. | 12-30-2010 |
20110024846 | LEAKAGE CONTROL IN FIELD EFFECT TRANSISTORS BASED ON AN IMPLANTATION SPECIES INTRODUCED LOCALLY AT THE STI EDGE - In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region. | 02-03-2011 |
20110049637 | BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES - Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material. | 03-03-2011 |
20110101469 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE - In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage. | 05-05-2011 |
20110291163 | Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth - In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors. | 12-01-2011 |
20120001174 | Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures - When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved. | 01-05-2012 |
20120025315 | Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region - The uniformity of transistor characteristics may be enhanced for transistors having incorporated therein a strain-inducing semiconductor material by using appropriately positioned dummy gate electrode structures. To this end, the dummy gate electrode structures may be positioned such that these structures may connect to or may overlap with the edge of the active region, thereby preserving a portion of the initial semiconductor material of the active region at the edge thereof upon forming the corresponding cavities. | 02-02-2012 |
20120153354 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP - When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented. | 06-21-2012 |
20120153401 | Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material - In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors. | 06-21-2012 |
20120156837 | Sacrificial Spacer Approach for Differential Source/Drain Implantation Spacers in Transistors Comprising a High-K Metal Gate Electrode Structure - In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor. | 06-21-2012 |
20120156846 | Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography - In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions. | 06-21-2012 |
20120161250 | Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for. | 06-28-2012 |
20120171830 | ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. | 07-05-2012 |
20120235249 | REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION - When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled. | 09-20-2012 |
20130062726 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 03-14-2013 |
20130065329 | Superior Integrity of High-K Metal Gate Stacks by Preserving a Resist Material Above End Caps of Gate Electrode Structures - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 03-14-2013 |
20130175577 | NFET Device with Tensile Stressed Channel Region and Methods of Forming Same - Disclosed herein is an NFET device with a tensile stressed channel region and various methods of making such an NFET device. In one example, the NFET transistor includes a semiconducting substrate, a first layer of semiconductor material positioned above the substrate, a second capping layer of semiconductor material positioned above the first layer of semiconductor material and a gate electrode structure positioned above the second capping layer of semiconductor material. | 07-11-2013 |
20130175585 | Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor - Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses. | 07-11-2013 |
20130178045 | Method of Forming Transistor with Increased Gate Width - Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess. | 07-11-2013 |
20130267044 | SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY PRESERVING A RESIST MATERIAL ABOVE END CAPS OF GATE ELECTRODE STRUCTURES - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 10-10-2013 |
20130313553 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 11-28-2013 |
20150034953 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 02-05-2015 |
20150054083 | STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL - An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain. | 02-26-2015 |